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MB90420/5 (A) SERIES F
Table 14-3 Function of Each Bit of LCDC Control Register Lower (LCRL)
Bit Name
bit 7
CSS: Clock select bit
bit 6
LCEN: Watch-mode-time
operation enable bit
bit 5
VSEL: LCD Driving power
control bit
bit 4
BK: Display/display blanking
select bit
bit 3
MS1, MS0: Display mode
bit 2
select bits
bit 1
FP1, FP0: Frame cycle
bit 0
select bits
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
This bit selects a frame cycle generation clock.
When this bit is 0, the main clock is selected. When this bit is 1, the sub-clock is
selected.
This bit enables an operation in the timer mode.
In the timer mode, an operation stops when this bit is 0, and an operation starts
when this bit is 1.
This bit selects whether to pass the current through the internal split resistors.
When this bit is 0, no current passes through the internal split resistors. When it
is 1, the current passes through the internal split resistors. When connecting
external split resistors, this bit must be set to 0.
Selects whether to display or blank LCD
When the LCD is blanked (BK = 1), segment output is nonselective waveform
(waveforms do not meet display condition).
These bits select duty of output waveform from three different duties
The common pin to be used is determined based on the selected duty output
mode.
When these bits are 0, the LCD controller or driver stops the display.
Note: Stop the display before the selected frame cycle generation clock stops
due to (for example) a transition to the stop mode.
Selects frame cycle for LCD display from four different frame cycles
Note: Calculate the optimum frame frequency for the LCD module to be used
and then set the register.
The frame frequency is influenced by the frequency of the original oscillation.
14-14
Function
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