Pwm 1&2 Select Registers - Fujitsu MB90420/5 (A) Series Hardware Manual

15.2.3 PWM 1&2 Select Registers
The PWM1 and PWM2 select registers select 0, 1, the PWM pulse, or high impedance for the external pin
output of the stepping motor controller.
n PWM 1&2 select registers
PWM1 select register
PWM2 select register
[bit 14] BS: Update bit
This bit is prepared to synchronize the settings for the PWM outputs. Any modifications in the two
compare registers and two select registers are not reflected to the output signals until this bit is set.
When this bit is set to "1", the PWM pulse generators and selectors load the register contents at the end
of the current PWM cycle. The BS bit is reset to "0" automatically at the beginning of the next PWM cycle.
If the BS bit is set to "1" by software at the same time as this automatic reset, the BS bit is set to "1" (or
remains unchanged) and the automatic reset is cancelled.
[bits 13 to 11] P2 to P0: Output select bits
These bits selects the output signal at PWM2P0.
[bits 10 to 8] M2 to M0: Output select bits
These bits selects the output signal at PWM2M0.
[bits 5 to 3] P2 to P0: Output select bits
These bits selects the output signal at PWM1P0.
[bits 2 to 0] M2 to M0: Output select bits
These bits selects the output signal at PWM1M0.
The following table shows the relationship between the output levels and select bits
P2
0
0
0
1
STEPPING MOTOR CONTROLLER
7 6
— — P2
— — R/W
— —
15 14 13
— BS P2
— R/W R/W
— 0
P1 P0 PWMnP0
0 0 L
0 1 H
1 X PWM pulses
X X High impedance
5 4 3
P1 P0
R/W R/W
0 0 0
12 11
P1 P0
R/W R/W
0 0 0
M2 M1
0 0
0 0
0 1
1 X
15-7
2 1 0
M2 M1 M0
R/W R/W R/W
0 0 0
10 9 8
M2 M1 M0
R/W R/W R/W
0 0 0
M0 PWMnM0
0 L
1 H
X PWM pulses
X High impedance