Fujitsu MB90420/5 (A) Series Hardware Manual page 6

Chapter 7 Mode Setting ....................................................................................................... 7-1
7.1 Mode Setting .............................................................................................................................. 7-3
7.2 Mode Pins (MD2 to MD0) ........................................................................................................... 7-4
7.3 Mode Data ................................................................................................................................... 7-5
Chapter 8 I/O Port................................................................................................................. 8-1
8.1 Overview of I/O Port................................................................................................................... 8-3
8.2 Registers and Assignment of Pins Serving as External Pins ............................................... 8-5
8.3 Port 0 ........................................................................................................................................... 8-6
8.3.1 Registers for Port 0 (PDR0, DDR0) ............................................................................... 8-8
8.3.2 Operation of Port 0 ......................................................................................................... 8-9
8.4 Port 1 ......................................................................................................................................... 8-11
8.4.1 Registers for Port 1 (PDR1, DDR1) ............................................................................. 8-13
8.4.2 Operation of Port 1 ....................................................................................................... 8-14
8.5 Port 3 ......................................................................................................................................... 8-16
8.5.1 Registers for Port 3 (PDR3, DDR3) ............................................................................. 8-18
8.5.2 Operation of Port 3 ....................................................................................................... 8-19
8.6 Port 4 ......................................................................................................................................... 8-21
8.6.1 Registers for Port 4 (PDR4, DDR4) ............................................................................. 8-23
8.6.2 Operation of Port 4 ....................................................................................................... 8-24
8.7 Port 5 ......................................................................................................................................... 8-26
8.7.1 Registers for Port 5 (PDR5, DDR5) ............................................................................. 8-28
8.7.2 Operation of Port 5 ....................................................................................................... 8-29
8.8 Port 6 ......................................................................................................................................... 8-31
8.8.1 Registers for Port 6 (PDR6, DDR6) ............................................................................. 8-33
8.8.2 Operation of Port 6 ....................................................................................................... 8-34
8.9 Port 7 ......................................................................................................................................... 8-36
8.9.1 Registers for Port 7 (PDR7, DDR7) ............................................................................. 8-38
8.9.2 Operation of Port 7 ....................................................................................................... 8-39
8.10 Port 8 ..................................................................................................................................... 8-41
8.10.1 Registers for Port 8 (PDR8, DDR8) ............................................................................. 8-43
8.10.2 Operation of Port 8 ....................................................................................................... 8-44
8.11 Port 9 ..................................................................................................................................... 8-46
8.11.1 Registers for Port 9 (PDR9, DDR9) ............................................................................. 8-48
8.11.2 Operation of Port 9 ....................................................................................................... 8-49
8.12 Program Example Using I/O Ports ..................................................................................... 8-51
Chapter 9 Watchdog Timer/Time-base Timer/Watch Timer (Sub-Clock) .......................... 9-1
9.1 Overview of Watchdog Timer, Time-base Timer, and Watch Timer ..................................... 9-3
9.2 Block Diagram of Watchdog Timer, Time-base Timer, and Watch Timer ............................ 9-4
9.3 List of Watchdog Timer, Time-base Timer, and Watch Timer Registers ............................. 9-5
9.3.1 Watchdog Timer Control Register (WDTC).................................................................. 9-6
9.3.2 Time-base Timer Control Register (TBTC) .................................................................. 9-8
9.3.3 Watch timer control register (WTC).............................................................................. 9-9
vi