Message Buffer Valid Register (Bvalr); Ide Register (Ider) - Fujitsu MB90420/5 (A) Series Hardware Manual

23.6.6 Message Buffer Valid Register (BVALR)

Message buffer valid register (BVALR) stores the validity of the message buffers (x) or displays their state.
n Message buffer valid register (BVALR)
Address: 000041 (CAN0)
H
Address: 000071 (CAN1)
H
Read/write →
Initial value →
Address: 000040 (CAN0)
H
Address: 000070 (CAN1)
H
Read/write →
Initial value →
0: Message buffer (x) invalid
1: Message buffer (x) valid
If the message buffer (x) is set to invalid, it will not transmit or receive messages.
If the buffer is set to invalid during transmission operating, it becomes invalid (BVALx = 0) after the
transmission is completed or terminated by an error.
If the buffer is set to invalid during reception operating, it immediately becomes invalid (BVALx = 0). If
received messages are stored in a message buffer (x), the message buffer (x) is invalid after storing the
messages.
Notes: • x indicates a message buffer number (x = 0 to 15).
• When invaliding a message buffer (x) by writing 0 to a bit (BVALx), execution of a bit manipulation
instruction is prohibited until the bit is set to 0.

23.6.7 IDE register (IDER)

This register stores the frame format used by the message buffers (x) during transmission/reception.
n IDE Register (IDER)
Address: 003C09 (CAN0)
H
Address: 003D09 (CAN1)
H
Read/write →
Initial value →
Address: 003C08 (CAN0)
H
Address: 003D08 (CAN1)
H
Read/write →
Initial value →
0: The standard frame format (ID11 bit) is used for the message buffer (x).
1: The extended frame format (ID29 bit) is used for the message buffer (x).
Note: This register should be set when the message buffer (x) is invalid (BVALx of the message buffer
valid register (BVALR) = 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary
received messages to be stored.
CAN CONTROLLER
15 14 13
BVAL15 BVAL14 BVAL13
(R/W) (R/W) (R/W)
(0) (0) (0)
7 6 5
BVAL7 BVAL6 BVAL5
(R/W) (R/W) (R/W)
(0) (0) (0)
15 14 13
IDE15 IDE14 IDE13
(R/W) (R/W) (R/W)
(X) (X) (X)
7 6 5
IDE7 IDE6 IDE5
(R/W) (R/W) (R/W)
(X) (X) (X)
23-19
12 11 10
BVAL12 BVAL11 BVAL10
(R/W) (R/W) (R/W)
(0) (0) (0)
4 3 2
BVAL4 BVAL3 BVAL2
(R/W) (R/W) (R/W)
(0) (0) (0)
12 11 10
IDE12 IDE11 IDE10
(R/W) (R/W) (R/W)
(X) (X) (X)
4 3 2
IDE4 IDE3 IDE2
(R/W) (R/W) (R/W)
(X) (X) (X)
← Bit No.
9 8
BVAL9 BVAL8
(R/W) (R/W)
(0) (0)
← Bit No.
1 0
BVAL1 BVAL0
(R/W) (R/W)
(0) (0)
← Bit No.
9 8
IDE9 IDE8
(R/W) (R/W)
(X) (X)
← Bit No.
1 0
IDE1 IDE0
(R/W) (R/W)
(X) (X)