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n Machine clock
The PLL clock output from the PLL multiplying circuit, the 2-divided clock of the original oscillation or 4-
divided clock of the sub-clock is the machine clock. This machine clock is supplied to the CPU and the
resources.
The main clock, the PLL clock or the sub-clock can be selected when the MCS bit or SCS bit of the CKSCR
is written to.
Figure 4.4 shows the state transition caused by switching the machine clock.
Main
MCS = 1
MCM = 1
SCS = 1
SCM = 1
CS1, CS0 = xx
(1)
"0" write to MCS bit
(2)
PLL Clock oscillation stabilization waiting termination & CS1, CS0 = 00
(3)
PLL Clock oscillation stabilization waiting termination & CS1, CS0 = 01
(4)
PLL Clock oscillation stabilization waiting termination & CS1, CS0 = 10
(5)
PLL Clock oscillation stabilization waiting termination & CS1, CS0 = 11
(6)
"1" write to MCS bit (The hardware standby and the watchdog reset included)
(7)
Synchronous timing of PLL clock and main clock
(8)
"0" write to SCS bit
(9)
Synchronous timing of main clock and sub-clock
(10) "1" write to SCS bit
(11) Main clock oscillation stabilization waiting termination
(12) Main clock oscillation stabilization waiting termination & CS1, CS0 = 00
(13) Main clock oscillation stabilization waiting termination & CS1, CS0 = 01
(14) Main clock oscillation stabilization waiting termination & CS1, CS0 = 10
(15) Main clock oscillation stabilization waiting termination & CS1, CS0 = 11
(16) "0" write to SCS bit
(17) Synchronous timing of PLL clock and main clock
MCS
MCM
SCM
SCS
CS1, CS0 : Multiplication rate select bit of clock select register (CKSCR)
Fig. 4.3 Transition Diagram of Machine Clock Selection State
Note:
The initial value of the machine clock is the main clock (CKSCR: MCS = 1, SCS = 1).
When SCS and MCS are both 0, SCS is preferred, and the sub-clock is selected.
(1)
(10)
(1)
(11)
(6)
(2)
Main → PLLx
MCS = 0
(3)
MCM = 1
(4)
MCS = 0
MCM = 1
(5)
(7)
CS1, CS0 = xx
PLL1 → Main
MCS = 1
MCM = 0
SCS = 1
SCM = 1
(7)
CS1, CS0 = 00
PLL2 → Main
MCS = 1
MCM = 0
SCS = 1
SCM = 0
(7)
CS1, CS0 = 01
PLL3 → Main
MCS = 1
MCM = 0
SCS = 1
SCM = 0
(7)
CS1, CS0 = 10
PLL4 → Main
MCS = 1
MCM = 0
SCS = 1
SCM = 0
(7)
CS1, CS0 = 11
: Machine clock select bit of clock select register (CKSCR)
: Machine clock display bit of clock select register (CKSCR)
: Machine clock display bit of clock select register (CKSCR) (sub)
: Machine clock select bit of clock select register (CKSCR) (sub)
CLOCK
Main → Sub
(9)
MCS = 1
MCM = 1
MCS = 0
MCM = 1
CS1, CS0 = xx
Sub → Main
(9)
MCS = 1
MCM = 1
MCS = 1
(12)
Sub → PLLx
MCM = 1
CS1, CS0 = xx
MCS = 0
(13)
MCM = 1
(14)
MCS = 0
MCM = 1
(15)
CS1, CS0 = xx
PLL1 → Sub
PLL1
multiplication
MCS = 1
MCS = 0
MCM = 0
(6)
(16)
MCM = 0
SCS = 1
CS1, CS0 = 00
SCM = 1
CS1, CS0 = 00
PLL2 → Sub
PLL2
multiplication
MCS = 1
MCS = 0
MCM = 0
(6)
(16)
MCM = 0
SCS = 1
CS1, CS0 = 01
SCM = 0
CS1, CS0 = 01
PLL3 → Sub
PLL3
multiplication
MCS = 1
MCS = 0
MCM = 0
(6)
(16)
MCM = 0
SCS = 1
CS1, CS0 = 10
SCM = 0
CS1, CS0 = 10
PLL4 → Sub
PLL4
multiplication
MCS = 1
MCS = 0
MCM = 0
(6)
(16)
MCM = 0
SCS = 1
CS1, CS0 = 11
SCM = 0
CS1, CS0 = 11
4-11
Sub
MCS = 1
(16)
MCM = 1
(10)
SCS = 0
SCM = 0
CS1, CS0 = xx
(17)
(17)
(17)
(17)
(17)
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