Table of Contents
Advertisement
• 0: Compare
Compare the bit of the acceptance code (ID register IDRx for comparing with the receive message ID)
corresponding to this bit with the bit of the received message ID. If there is no match, no message is
received.
• 1: Mask
Mask the bit of the acceptance code ID register (IDRx) corresponding to this bit. No comparison is made
with the bit of the receive message ID.
Note:
AMR0 and AMR1 should be set when all the message buffers (x) selecting AMR0 and AMR1 are
invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffers are
valid (BVALx = 1) may cause unnecessary received messages to be stored.
23.6.20 Message Buffers
There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register (IDRx), DLC register
(DLCRx), and data register (DTRx).
n Message buffers
• The message buffer (x) is used both for transmission and reception.
• The lower-numbered message buffers are assigned higher priority.
– At transmission, when a request for transmission is made to more than one message buffer,
transmission is performed from the lowest-numbered message buffer (See Section 23.7).
– At reception, when the receive message ID passes through the acceptance filter (mechanism for
comparing the acceptance-masked ID of receive message and message buffer) of more than one
message buffer, the received message is stored in the lowest-numbered message buffer (See Section
23.8).
• When the same acceptance filter is set in more than one message buffer, the message buffers can be
used as a multi-level message buffer. This provides allowance for receiving time (See Section 23.12).
Notes: • A write operation to message buffers and general-purpose RAM areas should be performed in
words to even addresses only. A write operation in bytes causes undefined data to be written to
the upper byte at writing to the lower byte. Writing to the upper byte is ignored.
• When the BVALx bit of the message buffer valid register (BVALR) is 0 (Invalid), the message
buffers x (IDRx, DLCRx, and DTRx) can be used as general-purpose RAM.
During the receive/transmit operation of the CAN controller, the CAN controller write/read to/from
the message buffers. If the CPU tries to write/read to/from the message buffers in this period, the
CPU may wait a maximum time of 64 machine cycles. This is also true for the general-purpose
RAM (CAN0: address 003A00
CAN CONTROLLER
to 003A1F
, and address 003B00
H
H
23-27
to 003B1F
).
H
H
Advertisement
Table of Contents
