Overview Of Low Voltage And Cpu Operation Detection Reset Circuit; Table 24-1 Detection Voltage Of Detection Reset Circuit For Low Voltage And Cpu Operation; Table 24-2 Interval Time For Cpu Operation Detection Reset Circuit - Fujitsu MB90420/5 (A) Series Hardware Manual

LOW VOLTAGE AND CPU OPERATION DETECTION RESET CIRCUIT
This chapter explains the function and operation of the detection reset circuit for low voltage and CPU
operation.

24.1 Overview of Low Voltage and CPU Operation Detection Reset Circuit

The low-voltage detection reset circuit monitors the power supply voltage and detects falls below the
detection voltage value. When a low voltage is detected, the low-voltage detection reset circuit causes an
internal reset.
The CPU operation detection reset circuit is a 20-bit counter that uses the original oscillation as the count
clock, and causes an internal reset if it is not cleared within a fixed period of time after starting.
n Low-voltage detection reset circuit
Table 24-1 shows the detection voltage.

Table 24-1 Detection Voltage of Detection Reset Circuit for Low Voltage and CPU Operation

When a low voltage is detected, the low-voltage detection flag (LVRC: LVRF) is set to 1 and an internal
reset is output.
The low-voltage detection reset circuit continues operating even in the Stop mode, so when it detects a low
voltage, it causes an internal reset and cancels the Stop mode.
A low voltage reset occurs after writing to the internal RAM. The reset output of this circuit is inhibited while
an internal reset occurs.
n CPU Operation detection reset circuit
The CPU operation detection reset circuit is a counter that prevents program runaway. The circuit starts
automatically after a power-on reset. After starting, the circuit must be cleared at regular intervals. An
internal reset occurs if the circuit is not cleared after a fixed time interval, because the program has entered
an endless loop for example.

Table 24-2 Interval Time for CPU Operation Detection Reset Circuit

*: The above values are obtained when the oscillation clock is 4 MHz.
This circuit stops in the CPU operation stop mode.
The conditions for clearing the counter of this circuit are given below:
1. Writing 0 to CL bit of LVRC register
2. Internal reset
3. Stopping main oscillation clock
4. Transition to sleep mode
5. Transition to time-base timer mode or timer mode
6. Starting hold
Detection Voltage
4.0 V ±0.3 V
Interval Time
About 262 ms
Oscillation Clock Cycle Count
20
2 cycle
24-3