Fujitsu MB90420/5 (A) Series Hardware Manual page 278

MB90420/5 (A) SERIES F
n Timer control status register (TCCSH/TCCSL)
Timer control status register
Address: 000029
H
Timer control status register
Address: 000028
H
[bit 15] ECKE
This bit selects the internal count clock source or the external count clock source of the 16-bit free-run
timer. The clock is changed immediately after writing to this bit, so change this bit when output compare
and input compare are in stop state.
Note: When an internal clock is selected, set bit 2 to bit 0 (CLK2 to CLK0) to the count clock. This count
clock is used as the base clock. Also, when inputting the clock from FRCK, set DDR: bit 7 = 0.
[bits 14, 13] Unused bits
[bits 12, 11, 10] MSI2, MSI1, MSI0
These bits set the count of masking the compare clear interrupt. These bits are composed of a 3-bit
reload counter that reloads the count value every time the count value becomes 000
is also loaded at writing to this register. The mask count is equal to the setting count (For example, when
masking is performed twice and the interrupt handling is performed at third times, 010
when 000 is set, the interrupt factor is not masked.
B
[bit 9] ICLR
This bit is the compare clear interrupt request flag. This bit is set to 1 when the value of the compare
clear register and the value of the 16-bit free-run timer match and the counter is cleared. An interrupt is
generated when the interrupt-request enable bit (bit 8: ICRE) is set. The ICLR bit is cleared when 0 is
written. Writing 1 to this bit has no meaning. The read-modify-write instructions always read 1 from this
bit.
[bit 8] ICRE
This bit is the compare clear interrupt enable bit. An interrupt is generated when the interrupt flag (bit 9:
ICLR) is set to 1 when the ICRE bit is 1.
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
bit 15 bit 14 bit 13
ECKE — —
(R/W) (R/W) (R/W)
(0) (—) (—)
bit 7 bit 6 bit 5
IVF IVFE STOP
(R/W) (R) (R/W)
(0) (0) (0)
0 Internal clock source selected
1 Clock input from the external pin (FRCK)
0 Interrupt request not issued
1 Interrupt request issued
0 Interrupt disabled
1 Interrupt enabled
bit 12 bit 11 bit 10
MSI2 MSI1 MSI0
(R/W) (R/W) (R/W)
(0) (0) (0)
bit 4 bit 3 bit 2
MODE SCLR CLK2
(R/W) (R/W) (R/W)
(0) (0) (0)
11-10
bit 9 bit 8
ICLR ICRE TCCS
(R/W) (R/W) ← Read/write
(0) (0)
← Initial value
bit 1 bit 0
CLK1 CLK0 TCCS
(R/W) (R/W)
← Read/write
(0) (0) ← Initial value
[Initial value]
. The counter value
B
is set.). However,
B
[Initial value]
[Initial value]