Reset Factor Bit; Fig. 3.7 Block Diagram Of Reset Factor Bit - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

3.5 Reset Factor Bit

The reset factor can be identified by reading the watchdog timer control register (WDTC).
n Reset factor bit
As shown in the Figure 3.7, each reset factor corresponds with a flip-flop. These data are obtained by
reading the watchdog timer control register (WDTC). When the reset factor needs to be identified after the
reset is cancelled, process the value read from WDTC using software, and then branch to the appropriate
program.
HSTX is fixed internally to H.
(Hardware standby mode is not available.)
Lowering of power
Power-on
supply voltage
Power-on reset Low power supply
detector voltage detector
Watchdog timer
control register
(WDTC)
S
F/F
O
S : Set
R : Reset
O : Output
F/F : Flip Flop
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
CPU Operation
detection, reset
request detector
Hardware standby
cancellation
detector
R S R
F/F
O

Fig. 3.7 Block Diagram of Reset Factor Bit

RSTX Pin
RSTX = L
External reset
request detector
S R S R
F/F F/F
O O
Internal data bus
3-10
RST bit set
No periodic clear
Detector for writing
Watchdog timer
to RST bit of
reset detector
LPMCR
Clear
S R
Delay circuit
F/F
O
The watchdog
timer control
register (WDTC)
is read.