System Control Register (Syscr) - Renesas F-ZTAT H8 Series Hardware Manual

17.2

System Control Register (SYSCR)

Bit 7
SSBY
Initial value 0
Read/Write R/W
Software standby
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
Bit 0: RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled
6 5
STS2 STS1 STS0
0 0
R/W R/W R/W
Standby timer select 2 to 0
4 3 2
UE NMIEG
0 1 0
R/W R/W
NMI edge select
User bit enable
Rev. 7.00 Sep 21, 2005 page 567 of 878
Section 17 RAM
1 0
— RAME
1 1
— R/W
RAM enable
Enables or
disables
on-chip RAM
Reserved bit
(Initial value)
REJ09B0259-0700