Block Diagram; Register Configuration - Renesas F-ZTAT H8 Series Hardware Manual

Section 17 RAM
17.1.1

Block Diagram

Figure 17.1 shows a block diagram of the on-chip RAM.
Legend
SYSCR: System control register
Note: * This example is of the H8/3048 operating in mode 7. The lower 20 bits of the address
are shown.
17.1.2

Register Configuration

The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of
SYSCR.
Table 17.1 System Control Register
Address* Name
H'FFF2 System control register
Note: * Lower 16 bits of the address.
Rev. 7.00 Sep 21, 2005 page 566 of 878
REJ09B0259-0700
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Bus interface
H'FEF10*
H'FEF12*
On-chip RAM
H'FFF0E*
Even addresses
Figure 17.1 RAM Block Diagram
SYSCR
H'FEF11*
H'FEF13*
H'FFF0F*
Odd addresses
Abbreviation R/W
SYSCR R/W
Initial Value
H'0B