Refresh Controller Bus Timing - Renesas F-ZTAT H8 Series Hardware Manual

Section 22 Electrical Characteristics
22.3.2

Refresh Controller Bus Timing

Refresh controller bus timing is shown as follows:
• DRAM bus timing
Figures 22.10 to 22.15 show the DRAM bus timing in each operating mode.
• PSRAM bus timing
Figures 22.16 and 22.17 show the pseudo-static RAM bus timing in each operating mode.
φ
t
AD
A to A
9 1
AS
t
RAD1
CS (RAS)
3
RD (CAS)
HWR (UW),
LWR ( LW
)
(read)
HWR (UW),
LWR ( LW
)
(write)
RFSH
D to D
15 0
(read)
D to D
15 0
(write)
Figure 22.10 DRAM Bus Timing (Read/Write): Three-State Access
Rev. 7.00 Sep 21, 2005 page 716 of 878
REJ09B0259-0700
T
1
t
AD
t
RAH
t
AS1
t
t
RAC
t
ASD
t
WDS3
— 2WE
T T
2 3
t
ASD
t
CAS
AS1
t
AA
t
CAC
t
RDS
WE Mode —
WE WE
t
RAD3
t
RP
t
SD
t
CRP
t
SD
t
WDH
t
RDH