Clock - Renesas F-ZTAT H8 Series Hardware Manual

Section 14 Smart Card Interface
14.3.5

Clock

As its serial communication clock, the smart card interface can use only the internal clock
generated by the on-chip baud rate generator. The bit rate can be selected by setting the bit rate
register (BRR) and bits CKS1 and CKS0 in the serial mode register (SMR). The bit rate can be
calculated from the equation given below. Table 14.5 lists some examples of bit rate settings.
If bit CKE0 is set to 1, a clock signal with a frequency equal to 372 times the bit rate is output
from the SCK pin.
0
B =
1488 × 2
where, N: BRR setting (0 ≤ N ≤ 255)
B: Bit rate (bits/s)
φ: System clock frequency (MHz)*
n: See table 14.4
Table 14.4 n-Values of CKS1 and CKS0 Settings
n
0
1
2
3
Note: * If the gear function is used to divide the system clock frequency, use the divided
frequency to calculate the bit rate. The equation above applies directly to 1/1 frequency
division.
Table 14.5 Bit Rates (bits/s) for Different BRR Settings (when n = 0)
N 7.1424
0 9600.0
1 4800.0
2 3200.0
Note: Bit rates are rounded off to one decimal place.
Rev. 7.00 Sep 21, 2005 page 522 of 878
REJ09B0259-0700
φ
× 10
6
× (N + 1)
2n–1
CKS1
0
0
1
1
10.00 10.7136
13440.9 14400.0
6720.4 7200.0
4480.3 4800.0
CKS0
0
1
0
1
φ φ φ φ (MHz)
13.00 14.2848
17473.1 19200.0
8736.6 9600.0
5824.4 6400.0
16.00 18.00
21505.4 24193.5
10752.7 12096.8
7168.5 8064.5