Erasing Flowchart And Sample Program - Renesas F-ZTAT H8 Series Hardware Manual

Section 19 Flash Memory (H8/3048F: Dual Power Supply (V
19.5.6

Erasing Flowchart and Sample Program

Flowchart for Erasing One Block
No
Address + 1 → address
Rev. 7.00 Sep 21, 2005 page 610 of 878
REJ09B0259-0700
Start
Write 0 data in all addresses
to be erased (prewrite) *1
n = 1
Set V E bit
PP
( V E bit = 1 in FLMCR)
PP
Wait (z) µs
Set erase block register
(set bit of block to be erased to 1)
Set top address in block
as verify address
Wait initial value setting x = 6.25 ms
*2
Enable watchdog timer
Select erase mode
(E bit = 1 in FLMCR)
Wait (x) ms
Clear E bit
Disable watchdog timer
Select erase-verify mode
(EV bit = 1)
*5
Wait (t ) µs
VS1
Dummy write to verify address *3
(flash memory latches address)
*5
Wait (t ) µs
VS2
*4
Verify (read memory)
OK
Last address?
Yes
Clear EV bit
Clear erase block register
(clear bit of erased block to 0)
Clear V E bit
PP
End of block erase
Figure 19.10 Erasing Flowchart
= 12 V))
PP
Notes: 1. Program all addresses to be
erased by following the prewrite
flowchart.
2. Set the watchdog timer overflow
interval to the value indicated in
table 19.10.
3. For the erase-verify dummy
write, write H'FF using a byte
transfer instruction.
4. Read to verify data from the
memory using a byte transfer
instruction.
: 4 µs
5. t
VS1
z:
t : 2 µs
VS2
N:
6. The erase time x is successively
incremented by the initial set
value × 2n
initial value of 6.25 ms or less
should be set, and the time for
one erasure should be 50 ms or
less.
Erasing ends
No good
Erase-verify ends
Clear EV bit
No
n ≥ N?
Yes
Clear erase block register
(clear bit of block to be
erased to 0)
Clear V E bit
PP
Erase error
5 to 10 µs
602
–1
(n = 1, 2, 3, 4). An
→ n
n + 1
Yes
n ≥ 5?
No
Double the erase time *6
(x × 2 → x)