Usage Notes - Renesas F-ZTAT H8 Series Hardware Manual

Bits 1 and 0—Divide (DIV1 and DIV0): These bits select the frequency division ratio, as
follows.
Bit 1: DIV1 Bit 0: DIV0
0 0
1
1 0
1
20.5.3

Usage Notes

The DIVCR setting changes the φ frequency, so note the following points.
• Select a frequency division ratio that stays within the assured operation range specified for the
clock cycle time t
cyc
limit of the clock frequency range. Avoid settings that give system clock frequencies less than
the lower limit.
Table 20.5 shows the comparison with the clock frequency range for each version.
Table 20.5 Comparison with the Clock Frequency Ranges in the H8/3048 Group
ROM type
Product type
Guaranteed 4.5–5.5 V
clock
3.15–5.5 V
frequency
2.7–5.5 V
range
Crystal oscillation range
• All on-chip module operations are based on φ. Note that the timing of timer operations, serial
communication, and other time-dependent processing differs before and after any change in
the division ratio. The waiting time for exit from software standby mode also changes when
the division ratio is changed. For details, see section 21.4.3, Selection of Waiting Time for Exit
from Software Standby Mode.
Frequency Division Ratio
1/1
1/2
1/4
1/8
in the AC electrical characteristics. Note that φ
F-ZTAT ZTAT
H8/3048F H8/3048
1–16 MHz 1–18 MHz
— 1–13 MHz
1–8 MHz 1–8 MHz
2–16 MHz 2–18 MHz
Section 20 Clock Pulse Generator
MIN
Mask ROM
H8/3048 H8/3047
Mask ROM Mask ROM
Version Version
1–18 MHz
1–13 MHz
1–8 MHz
2–18 MHz
Rev. 7.00 Sep 21, 2005 page 661 of 878
(Initial value)
must be in the lower
H8/3045 H8/3044
Mask ROM Mask ROM
Version Version
REJ09B0259-0700