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Control Signal Timing - Renesas F-ZTAT H8 Series Hardware Manual

16-bit single-chip microcomputer
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22.3.3

Control Signal Timing

Control signal timing is shown as follows:
• Reset input timing
Figure 22.18 shows the reset input timing.
• Reset output timing
Figure 22.19 shows the reset output timing.
• Interrupt input timing
Figure 22.20 shows the input timing for NMI and IRQ
• Bus-release mode timing
Figure 22.21 shows the bus-release mode timing.
φ
RES
MD2 to MD0
φ
RESO
Note: * This is a function for models with on-chip mask ROM (H8/3048, H8/3047, H8/3045, and
H8/3044), PROM (H8/3048ZTAT), and on-chip flash memory with a dual power supply
(H8/3048F). The function does not exist in the product with on-chip flash memory with a
single power supply (H8/3048F-ONE).
t
RESS
t
MDS
Figure 22.18 Reset Input Timing
t
RESD
Figure 22.19 Reset Output Timing*
Section 22 Electrical Characteristics
to IRQ
.
5
0
t
RESS
t
RESW
t
RESD
t
RESOW
Rev. 7.00 Sep 21, 2005 page 721 of 878
REJ09B0259-0700

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