Usage Notes - Renesas F-ZTAT H8 Series Hardware Manual

14.4

Usage Notes

When using the SCI as a smart card interface, note the following points.
Receive Data Sampling Timing in Smart Card Mode and Receive Margin: In smart card
mode the SCI operates on a base clock with 372 times the bit rate frequency. In receiving, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the 186th base clock pulse. See figure 14.10.
Internal
base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 14.10 Receive Data Sampling Timing in Smart Card Mode
The receive margin can therefore be expressed as follows.
Receive margin in smart card mode:
M =
0.5 –
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 372)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute deviation of clock frequency
372 clocks
186 clocks
0 185
Start
bit
1
– (L – 0.5) F –
2N
371 0
D0
D – 0.5
(1 + F) × 100%
N
Rev. 7.00 Sep 21, 2005 page 531 of 878
Section 14 Smart Card Interface
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REJ09B0259-0700
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