Figure 6.18-3 Endpoint Sram Structure; Figure 6.18-4 Setup Transaction Followed By Data In Transaction - Nuvoton ISD94124BYI Technical Reference Manual

BUFSEG0 = 0x008
BUFSEG1 = 0x048
BUFSEG2 = 0x088
BUFSEG3 = 0x100
6.18.5.8 Handling Transactions with USB Device Peripheral
User can use interrupt or polling USBD_INTSTS to monitor the USB transactions. When
transactions occur, USBD_INTSTS will be set by hardware and send an interrupt request to CPU
(if related interrupt enabled), or user can polling USBD_INTSTS to get these events without
interrupt. The following is the control flow with interrupt enabled.
When USB host has requested data from a device controller, user needs to prepare related data in
the specified endpoint buffer in advance. After buffering the required data, user needs to write the
actual data length in the specified USBD_MXPLDx register. Once this register is written, the internal
signal "In_Rdy" will be asserted and the buffering data will be transmitted immediately after
receiving associated IN token from Host. Note that after transferring the specified data, the signal
"In_Rdy" will de-assert automatically by hardware.
Setup Received
USB
SETUP PID Data Setup
Bus Packets
USB_IRQ
In_Rdy

Figure 6.18-4 Setup Transaction Followed by Data IN Transaction

Sep 9, 2019
ISD94100 Series Technical Reference Manual
USB SRAM Start Address
Setup Token Buffer: 8 bytes
EP0 SRAM Buffer: 64 bytes
EP1 SRAM Buffer: 64 bytes
EP2 SRAM Buffer
EP3 SRAM Buffer

Figure 6.18-3 Endpoint SRAM Structure

Setup Handled by Firmware
ACK PID IN PID
Set by Hardware Clear by Firmware
Page 837 of 928
USBD_SRAM = USBD_BA + 0x0100h
EP0 SA = USBD_BA + 0x0108h
MXPLD0 = 0x40
EP1 SA = USBD_BA + 0x0148h
MXPLD1 = 0x40
EP2 SA = USBD_BA + 0x0188h
EP3 SA = USBD_BA + 0x0200h
Data In
NAK PID IN PID Data 0/1
Set by writing
Clear by Hardware
USBD_MXPLDx
register
1K
Bytes
ACK PID
Rev1.09