Register Description - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc

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Register Description

PWM Control Register 0

PWM0_BA+0x00

ISD94100 Series Technical Reference Manual

R/W Description

R/W PWM Control Register 0

ICE Debug Mode Acknowledge Disable (Write Protected)

0 = ICE debug mode acknowledgement effects PWM output.

PWM pin will be forced as tri-state while ICE debug mode acknowledged.

1 = ICE debug mode acknowledgement disabled.

PWM pin will keep output no matter ICE debug mode acknowledged or not.

Note: This register is write protected. Refer to SYS_REGLCTL register.

ICE Debug Mode Counter Halt (Write Protected)

If counter halt is enabled, PWM all counters will keep current value until exit ICE debug

0 = ICE debug mode counter halt disable.

1 = ICE debug mode counter halt enable.

Note: This register is write protected. Refer to SYS_REGLCTL register.

Reserved. Any values read should be ignored. When writing to this field always write with

reset value.

Group Function Enable Bit(S)

0 = The output waveform of each PWM channel are independent.

1 = Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and

unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1.

Reserved. Any values read should be ignored. When writing to this field always write with

reset value.

PWM Channel 5 Immediately Load Enable Bits

0 = PERIOD will load to PBUF at the end point of each period. CMPDAT will load to

CMPBUF at the end point or center point of each period by setting CTRLD bit.

1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update

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