Figure 6.13-29 Eeprom Random Read - Nuvoton ISD94124BYI Technical Reference Manual

2
6.13.5.4.15 I C Bus Management Status Register (I2C_BUSSTS)
Monitor the PECDONE
(I2C_BUSSTS[2]) for PEC control flow.
Monitor the SCTLDIN (I2C_BUSSTS[4]) for I2Cn_SMBSUS input status.
2
6.13.5.4.16 I C Byte Number Register (I2C_PKTSIZE)
When the PECEN bit (I2C_BUSCTL[1]) is set. The I
data on the bus. The PLDSIZE (I2C_PKTSIZE[8:0]) is used to define the data number in the bus.
When the counter reach the value of PLDSIZE, the final PEC value will be transmitted or received
automatically when the PECTXEN bit (I2C_BUSCTL[8]) is set.
2
6.13.5.4.17 I C PEC VALUR Register (I2C_PKTCRC)
The register indicates the calculated PECCRC (I2C_PKTCRC[7:0]) value of data on the I
The detail of information is defined the PEC section of SM Bus.
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6.13.5.4.18 I C Bus Management Timer and I
I2C_CLKTOUT)
Both of the definitions of these registers are described in the time-out section of SM Bus.
6.13.5.5 Example for Random Read on EEPROM
The following steps are used to configure the I
from EEPROM.
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1. Set I C0 the multi-function pin by GPIO multiple function control registers.
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2. Enable I C0 APB clock, I2C0CKEN=1 in the "CLK_APBCLK0" register.
3. Set I2C0RST=1 to reset I
I2C0RST=0 in the "SYS_IPRST1" register.
4. Set I2CEN=1 to enable I
2
5. Give I C0 clock a divided register value for I
6. Set SETENA=0x00000040 in the "NVIC_ISER2" register to set I
7. Set INTEN=1 to enable I
8. Set I 2 C0 address registers "I2C_ADDR0 ~ I2C_ADDR3".
Random read operation is one of the methods of access EEPROM. The method allows the master
to access any address of EEPROM space. Figure 6.13-29 shows the EEPROM random read
operation.
SLA+W
S
SDA
A
T 1 0 1 0
LINE 2
A
Figure 6.13-30 shows how to use I
Sep 9, 2019
ISD94100 Series Technical Reference Manual
(I2C_BUSSTS[7]),
2
2
2
C0 controller then set I
2
C0 controller in the "I2C_CTL" register.
2
C0 Interrupt in the "I2C_CTL" register.
ROM ADDRRSS ROM ADDRRSS
HIGH BYTE
LOW BYTE
A A
A A
W C X X X C
1 0
K K

Figure 6.13-29 EEPROM Random Read

2
C controller to implement the protocol of EEPROM random read.
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BCDONE (I2C_BUSSTS[1])
2 C controller will calculate the PEC value of the
C Clock Low Timer Register (I2C_BUSTOUT/
C0 related registers when using I
2
C0 controller to normal operation,
2
C clock rate in the "I2C_CLKDIV".
2
C0 IRQ.
SLA+R DATA BYTE
A A
S A A A
C 1 0 1 0 R C
T 2 1 0
K K
or PECERR
2 C bus.
2
C to read data
N S
A T
C O
K
Rev1.09