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The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of ISD ARM® Cortex®-M0 microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.
ISD91200 Series Technical Reference Manual Table of Contents- TABLE OF CONTENTS- ......................2 GENERAL DESCRIPTION ....................11 FEATURES ........................12 PART INFORMATION AND PIN CONFIGURATION ............16 Pin Configuration ....................16 Pin Description ....................... 17 BLOCK DIAGRAM ......................22 FUNCTIONAL DESCRIPTION..................23 ®...
ISD91200 Series Technical Reference Manual GENERAL DESCRIPTION The ISD91200 series is a system-on-chip product optimized for low power, audio record and playback with an embedded ARM® Cortex™-M0 32-bit microcontroller core. The ISD91200 device embeds a Cortex™-M0 core running up to 50 MHz with 64K/128Kbyte of non- volatile flash memory and 12K-byte of embedded SRAM.
ISD91200 Series Technical Reference Manual FEATURES • Core – ARM® Cortex™-M0 core running up to 50 MHz for normal speed. – One 24-bit System tick timer for operating system support. – Supports a variety of low power sleep and power down modes.
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ISD91200 Series Technical Reference Manual • Audio Analog to Digital converter – Sigma Delta ADC with configurable decimation filter and 16 bit output. – 90dB Signal-to-Noise (SNR) performance. – Programmable gain amplifier with 32 steps from -12 to 35.25dB in 0.75dB steps.
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ISD91200 Series Technical Reference Manual – Full duplex synchronous serial data transfer – Variable length of transfer data from 1 to 4 bytes – MSB or LSB first data transfer – 2 slave/device select lines when used in master mode.
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ISD91200 Series Technical Reference Manual – Digital Microphone interface. • Standby current in STOP mode with SRAM retention <=10µA at 25°C. • Operating Temperature: -40C~85C • Package: – All Green package (RoHS) LQFP 64-pin Release Date: Sep 16, 2019 - 15 - Revision 2.4...
ISD91200 Series Technical Reference Manual Pin Description The ISD91200 is a low pin count device where many pins are configurable to alternative functions. All General Purpose Input/Output (GPIO) pins can be configured to alternate functions as described in the table below.
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ISD91200 Series Technical Reference Manual Pin No. Pin Name Pin Type Alt CFG Description LQFP SPI1_SSB Slave Select Bar for SPI1 interface PA.7 General purpose input/output pin; Port A, bit 7 UART0_RX Receive channel of UART 0 I2C0_SCL Serial Clock, I2C interface...
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ISD91200 Series Technical Reference Manual Pin No. Pin Name Pin Type Alt CFG Description LQFP PA.15 General purpose input/output pin; Port A, bit 15 UART1_RX Receive channel of UART 1 MCLK Master clock output for synchronizing external device XO32K 32.768kHz Crystal Oscillator Output ICE_DAT Serial Wire Debug port clock pin.
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ISD91200 Series Technical Reference Manual Pin No. Pin Name Pin Type Alt CFG Description LQFP Operational Amplifier 1 positive input PB.4 General purpose input/output pin, analog capable; Port B, bit 4 I2S0_FS Frame Sync Clock for I2S interface Touch scan channel 4 Operational Amplifier 1 negative input PB.5...
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ISD91200 Series Technical Reference Manual Pin No. Pin Name Pin Type Alt CFG Description LQFP CMP2 Compare 2 Output I2S0_SDO Serial Data Output for I2S interface UART1_RX Receive channel of UART 1 CS11 Touch scan channel 11 SAR3 SARADC channel 3 PB.12...
ISD91200 Series Technical Reference Manual FUNCTIONAL DESCRIPTION ® Cortex™-M0 core The Cortex™-M0 processor is a multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface and includes an NVIC component. It also has hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processor.
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ISD91200 Series Technical Reference Manual – Two watchpoints. – Program Counter Sampling Register (PCSR) for non-intrusive code profiling. – Single step and vector catch capabilities. • Bus interfaces: – Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals and memory.
ISD91200 Series Technical Reference Manual System Manager 5.2.1 Overview The following functions are included in system manager section System Memory Map System Timer (SysTick) Nested Vectored Interrupt Controller (NVIC) System management registers for product ID ...
ISD91200 Series Technical Reference Manual 5.2.3 System Power Distribution The ISD91200 implements several power domains: Analog power from VCCA and VSSA provides the power for analog module operation. Digital power from VCCD and VSSD supplies the power to the IO ring and the internal regulator which provides 1.5V power for digital operation.
ISD91200 Series Technical Reference Manual 5.2.4 System Memory Map The ISD91200 provides 4G-byte address space. The memory locations assigned to each on-chip module is shown in Table 5-1. The detailed register definition, memory space, and programming detailed will be described in the following sections for each on-chip module. The ISD91200 supports little-endian data format.
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ISD91200 Series Technical Reference Manual 0x400B_00A0 - 0x400B_00AF VOLCTRL_BA Volume Control Registers 5.16.2 0x400D_0000 – 0x400D_3FFF CSCAN_BA CAP SENSE Control Registers 7.6.6 0x400E_0000 – 0x400E_FFFF SDADC_BA Analog-Digital-Converter (ADC) Registers 7.1.5 0x400F_0000 – 0x400F_7FFF SBRAM_BA Standby RAM Block Address space System Control Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 –...
ISD91200 Series Technical Reference Manual 5.2.5 System Manager Control Registers Register Offset Description Reset Value SYS Base Address: SYS_BA = 0x5000_0000 SYS_PDID SYS_BA+0x00 Product ID 0xXXXX_XXXX SYS_RSTSTS SYS_BA+0x04 System Reset Source Register 0x0000_0XXX SYS_IPRST0 SYS_BA+0x08 IP Reset Control Resister0 0x0000_0000...
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ISD91200 Series Technical Reference Manual Product Identifier Register (SYS_PDID) This register provides specific read-only information for software to identify this chip. Register Offset Description Reset Value SYS_PDID SYS_BA+0x00 Product ID 0xXXXX_XXXX PDID[31:24] PDID[23:16] PDID[15:8] PDID[7:0] Table 5-2 System Product Identifier Register (SYS_PDID, address 0x5000_0000) Bit Description.
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ISD91200 Series Technical Reference Manual System Reset Source Register (SYS_RSTSTS) This register provides specific information for software to identify this chip’s reset source from last operation. Register Offset Description Reset Value SYS_RSTSTS SYS_BA+0x04 System Reset Source Register 0x0000_0XXX Reserved Reserved...
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ISD91200 Series Technical Reference Manual Reset Source From CPU The CPURF flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) with a “1” to reset Cortex-M0 CPU kernel and Flash memory controller (FMC). CPURF 0= No reset from CPU.
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ISD91200 Series Technical Reference Manual IP Reset Control Register1(SYS_IPRST0) Register Offset Description Reset Value SYS_IPRST0 SYS_BA+0x08 IP Reset Control Resister0 0x0000_0000 Reserved PDMARST CPURST CHIPRST Table 5-4 IP Reset Control Register 1 (SYS_IPRST0 address 0x5000_0008) Bit Description. Bits Description [31:3] Reserved Reserved.
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ISD91200 Series Technical Reference Manual IP Reset Control Register1 (SYS_IPRST1) Setting these bits “1” will generate an asynchronous reset signal to the corresponding peripheral block. The user needs to set bit to “0” to release block from the reset state.
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ISD91200 Series Technical Reference Manual GPIOA Input Type Control Register (SYS_GPSMTEN) Register Offset Description Reset Value SYS_GPSMTEN SYS_BA+0x30 GPIOA/B input type control register 0xFFFF_0000 HSGPBG3 SSGPBG3 HSGPBG2 SSGPBG2 HSGPBG1 SSGPBG1 HSGPBG0 SSGPBG0 HSGPAG3 SSGPAG3 HSGPAG2 SSGPAG2 HSGPAG1 SSGPAG1 HSGPAG0 SSGPAG0...
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ISD91200 Series Technical Reference Manual this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. SSGPBG1 Each bit controls a group of four GPIO pins [26] 1 = GPIOB 7/6/5/4 input Schmitt Trigger enabled.
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ISD91200 Series Technical Reference Manual this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. HSSGPAG0 Each bit controls a group of four GPIO pins [17] 1 = GPIOA 3/2/1/0 Output high slew rate.
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ISD91200 Series Technical Reference Manual GPIO Alternative Function Control Register (SYS_GPA_MFP, SYS_GPB_MFP) Each GPIO pin can take on multiple alternate functions depending on the setting of this register. Each pin has two bits of alternate function control. Set to 00 the pin is a standard GPIO pin whose attributes are defined by the GPIO control registers (See Section 0).
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ISD91200 Series Technical Reference Manual Alternate Function Setting for PA11MFP 00 = GPIO. [23:22] PA11MFP 01 = PWM0CH1. 10 = TM1. 11 = DPWM_M. Alternate Function Setting for PA10MFP 00 = GPIO. [21:20] PA10MFP 01 = PWM0CH0. 10 = TM0.
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ISD91200 Series Technical Reference Manual Alternate Function Setting for PA2MFP 00 = GPIO. [5:4] PA2MFP 01 = SPI0_SCLK0. 10 = DMIC_DAT. 11 = I2S0_SDI Alternate Function Setting for PA1MFP 00 = GPIO. [3:2] PA1MFP 01 = SPI0_MOSI0. 11 = I2S0_BCLK.
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ISD91200 Series Technical Reference Manual Alternate Function Setting for PB13MFP 00 = GPIO. [27:26] PB13MFP 01 = SPI0_MOSI0. 10 = SPI1_SCLK. 11 = SARADC_TRIG. Alternate Function Setting for PB12MFP 00 = GPIO. [25:24] PB12MFP 01 = SP0_MISO1. 10 = SPI1_MOSI.
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ISD91200 Series Technical Reference Manual Alternate Function Setting for PB2MFP [5:4] PB2MFP 00 = GPIO. 01 = SPI1_SSB. Alternate Function Setting for PB1MFP [3:2] PB1MFP 00 = GPIO. 01 = SPI1_SCLK. Alternate Function Setting for PB0MFP [1:0] PB0MFP 00 = GPIO.
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ISD91200 Series Technical Reference Manual Protected Register Lock Key Register (SYS_REGLCTL) Certain critical system control registers are protected against inadvertent write operations which may disturb chip operation. These system control registers are locked after power on reset until the user specifically issues an unlock sequence to open the lock.
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ISD91200 Series Technical Reference Manual Oscillator Trim Control Register (SYS_IRCTCTL) The master oscillator of the I91200 has an adjustable frequency and can be controlled by the SYS_IRCTCTL register. This register contains the current scillator frequency trim value, which depends upon the setting of register CLK_CLKSEL0.HIRCFSEL register. If this register is 0, SYS_OSCTRIM0 trim is active, if 1 then SYS_OSCTRIM1 is active, if 2 then SYS_OSCTRIM2.
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ISD91200 Series Technical Reference Manual 10kHz Oscillator Trim Register (SYS_OSC10KTRIM) Register Offset Description Reset Value SYS_OSC10KTRIM SYS_BA+0x114 R/W 10kHz Oscillator (LIRC) Trim Register 0xXXXX_XXXX TRMCLK Reserved Reserved Reserved TRIM TRIM TRIM Bits Description [31] TRMCLK Must be toggled to( from 0 => 1 => 0) load a new OSC10K_TRIM...
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ISD91200 Series Technical Reference Manual Oscillator Trim 0 Control Register (SYS_OSCTRIM0) Register Offset R/W Description Reset Value SYS_OSCTRIM0 SYS_BA+0x118 R/W Internal oscillator trim register 0 0xXXXX_XXXX EN2MHZ Reserved Reserved TRIM TRIM Table 5-13 Oscillator Frequency Adjust Control Register (OSCTRIM0, address 0x5000_0118).
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ISD91200 Series Technical Reference Manual Oscillator Trim 1 Control Register (SYS_OSCTRIM1) Register Offset R/W Description Reset Value SYS_OSCTRIM1 SYS_BA+0x11C R/W Internal oscillator trim register 1 0xXXXX_XXXX EN2MHZ Reserved Reserved TRIM TRIM Table 5-14 Oscillator Frequency Adjust Control Register (OSCTRIM1, address 0x5000_011C).
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ISD91200 Series Technical Reference Manual Oscillator Trim 2 Control Register (SYS_OSCTRIM2) Register Offset R/W Description Reset Value SYS_OSCTRIM2 SYS_BA+0x120 R/W Internal oscillator trim register 2 0xXXXX_XXXX EN2MHZ Reserved Reserved TRIM TRIM Table 5-15 Oscillator Frequency Adjust Control Register (OSCTRIM, address 0x5000_0120).
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ISD91200 Series Technical Reference Manual XTAL32K Oscillator Control Register (SYS_XTALTRIM) Register Offset R/W Description Reset Value SYS_XTALTRIM SYS_BA+0x124 R/W External Crystal oscillator trim register 0xXXXX_XXXX Reserved Reserved SELXT Reserved LOWPWR Reserved Reserved Reserved Reserved Table 5-16 Xtal Trim Bits Description...
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ISD91200 Series Technical Reference Manual Reserved Register Offset R/W Description Reset Value Reserved R/W System reserved, keep POR value 0xXXXX_XXXX SYS_BA+0x128 Reserved Reserved Reserved Reserved Table 5-17 Factory Default Bits Description [31:0] Reserved This register is loaded with trim from manufacturing – do not modify.
ISD91200 Series Technical Reference Manual 5.2.6 System Timer (SysTick) The Cortex-M0 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ...
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ISD91200 Series Technical Reference Manual SysTick Control and Status (SYST_CSR) Register Offset Description Reset Value SYST_CSR SYSTICK_BA+0x10 R/W SysTick Control and Status Register 0x0000_0000 Table 5-18 SysTick Control and Status Register (SYST_CSR, address 0xE000_E010) Reserved Reserved COUNTFLAG Reserved Reserved CLKSRC...
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ISD91200 Series Technical Reference Manual SysTick Reload Value Register (SYST_RVR) Register Offset Description Reset Value SYST_RVR SYSTICK_BA+0x14 R/W SysTick Reload value Register 0xXXXX_XXXX Table 5-19 SysTick (SYST_RVR, address 0xE000_E014) Reload Value Register Reserved RELOAD[23:16] RELOAD[15:8] RELOAD[7:0] Bits Description [31:24] Reserved...
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ISD91200 Series Technical Reference Manual SysTick Current Value Register (SYST_CVR) Register Offset Description Reset Value SYST_CVR SYSTICK_BA+0x18 R/W SysTick Current value Register 0xXXXX_XXXX Table 5-20 SysTick Current Value Register (SYST_CVR, address 0xE000_E018) Reserved CURRENT [23:16] CURRENT [15:8] CURRENT[7:0] Bits Description...
5.2.7.1 Exception Model and System Interrupt Map The following table lists the exception model supported by ISD91200 series. Software can set four levels of priority on certain exceptions as well as on all interrupts. The highest user-configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the user- configurable interrupts is “0”.
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ISD91200 Series Technical Reference Manual Table 5-21 Exception Model Exception Name Vector Number Priority Reset Hard Fault Reserved 4 ~ 10 SVCall Configurable Reserved 12 ~ 13 PendSV Configurable SysTick Configurable Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable Table 5-22 System Interrupt Map...
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ISD91200 Series Technical Reference Manual 5.2.7.3 Operation Description NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the interrupt will not activate.
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ISD91200 Series Technical Reference Manual 5.2.7.4 NVIC Control Registers R: read only, W: write only, R/W: both read and write, W&C: Write 1 clear Register Offset Description Reset Value SCS Base Address: SCS_BA = 0xE000_E100 NVIC_ISER SCS_BA+0x000 IRQ0 ~ IRQ31 Set-Enable Control Register...
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ISD91200 Series Technical Reference Manual ( ) IRQ0 ~ IRQ31 Set-Enable Control Register NVIC_ISER Register Offset Description Reset Value NVIC_ISER SCS_BA+0x000 R/W IRQ0 ~ IRQ31 Set-Enable Control Register 0x0000_0000 If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.
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ISD91200 Series Technical Reference Manual IRQ0 ~ IRQ31 Clear-Enable Control Register (NVIC_ICER) Register Offset Description Reset Value NVIC_ICER SCS_BA+0x080 R/W IRQ0 ~ IRQ31 Clear-Enable Control Register 0x0000_0000 Table 5-25 Interrupt Clear-Enable Control Register (ICER, address 0xE000_E180) Bit Description Bits Description Clear-enable Control Disable one or more interrupts within a group of 32.
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ISD91200 Series Technical Reference Manual IRQ0 ~ IRQ31 Set-Pending Control Register (NVIC_ISPR) Register Offset Description Reset Value NVIC_ISPR SCS_BA+0x100 R/W IRQ0 ~ IRQ31 Set-Pending Control Register 0x0000_0000 Table 5-26 Interrupt Set-Pending Control Register (ISPR, address 0xE000_E200) Bits Description Set-pending Control Writing 1 to a bit forces pending state of the associated interrupt under software control.
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ISD91200 Series Technical Reference Manual IRQ0 ~ IRQ31 Clear-Pending Control Register (NVIC_ICPR) Register Offset Description Reset Value NVIC_ICPR SCS_BA+0x180 R/W IRQ0 ~ IRQ31 Clear-Pending Control Register 0x0000_0000 Table 5-27 Interrupt Clear-Pending Control Register (ICPR, address 0xE000_E280) Bits Description Clear-pending Control Writing 1 to a bit to clear the pending state of associated interrupt under software control.
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ISD91200 Series Technical Reference Manual 5.2.7.5 Interrupt Source Control Registers Along with the interrupt control registers associated with the NVIC, the ISD91200 also implements some specific control registers to facilitate the interrupt functions, including “interrupt source identify”, ”NMI source selection” and “interrupt test mode”. They are described as below.
ISD91200 Series Technical Reference Manual 5.2.8 System Control Registers Key control and status features of Coterx-M0 are managed centrally in a System Control Block within the System Control Registers. For more detailed information, please refer to the documents “ARM® Cortex™-M0 Technical Reference Manual”...
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ISD91200 Series Technical Reference Manual CPUID Base Register (SYSINFO_CPUID) Register Offset R/W Description Reset Value SYSINFO_CPUID SYSINFO_BA+0x000 CPUID Base Register 0x410C_C200 IMPCODE Reserved PART PARTNO[11:4] PARTNO[3:0] REVISION Bits Description Implementer Code Assigned by ARM [31:24] IMPCODE ARM = 0x41. [23:20] Reserved Reserved.
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ISD91200 Series Technical Reference Manual Interrupt Control State Register (SYSINFO_ICSR) Register Offset Description Reset Value SYSINFO_ICSR SYSINFO_BA+0x004 Interrupt Control State Register 0x0000_0000 NMIPNSET Reserved PPSVISET PPSVICLR PSTKISET PSTKICLR Reserved ISRPREEM ISRPEND Reserved VTPNDING[8:4] VTPEND[3:0] Reserved VTACT[8] VTACT[7:0] Bits Description NMI Pending Set Control...
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ISD91200 Series Technical Reference Manual Vector Active [8:0] VTACT 0: Thread mode Value > 1: the exception number for the current executing exception. Release Date: Sep 16, 2019 - 106 - Revision 2.4...
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ISD91200 Series Technical Reference Manual Application Interrupt and Reset Control Register (SYSINFO_AIRCTL) Register Offset Description Reset Value SYSINFO_AIRCTL SYSINFO_BA+0x00C R/W Application Interrupt and Reset Control Register 0xFA05_0000 VTKEY VTKEY ENDIANES Reserved Reserved SRSTREQ CLRACTVT Reserved Bits Description Vector Key The value 0x05FA must be written to this register, otherwise...
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ISD91200 Series Technical Reference Manual System Control Register (SYSINFO_SCR) Register Offset Description Reset Value SYSINFO_SCR SYSINFO_BA+0x010 System Control Register 0x0000_0000 Reserved Reserved Reserved Reserved SEVNONPN Reserved SLPDEEP SLPONEXC Reserved Bits Description [31:5] Reserved Send Event on Pending Bit 0 = only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded.
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ISD91200 Series Technical Reference Manual System Handler Priority Register2 (SYSINFO_SHPR2) Register Offset Description Reset Value SYSINFO_SHPR2 SYSINFO_BA+0x01C System Handler Priority Register 2 0x0000_0000 PRI11 Reserved Reserved Reserved Reserved Bits Description Priority of System Handler 11 – SVCall [31:30] PRI11 “0” denotes the highest priority and “3” denotes lowest priority...
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ISD91200 Series Technical Reference Manual System Handler Priority Register3 (SYSINFO_SHPR3) Register Offset Description Reset Value SYSINFO_SHPR3 SYSINFO_BA+0x020 System Handler Priority Register 3 0x0000_0000 PRI15 Reserved PRI14 Reserved Reserved Reserved Bits Description Priority of System Handler 15 – SYST [31:30] PRI15 “0”...
ISD91200 Series Technical Reference Manual Clock Controller and Power Management Unit (PMU) The clock controller generates the clock sources for the whole device, including all AMBA interface modules and all peripheral clocks. Clock gating is provided on all peripheral clocks to minimize power consumption.
ISD91200 Series Technical Reference Manual 5.3.2 System Clock & SysTick Clock The system clock has 4 clock sources from clock generator block. The clock source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The clock is then divided by HCLKDIV+1 to produce the master clock for the device.
ISD91200 Series Technical Reference Manual 5.3.3 Peripheral Clocks Each peripheral has a selectable clock gate. The register CLK_APBCLK0 determines whether the clock is active for each peripheral. In addition, the CLK_SLEEPCTL register determines whether these clocks remain on during M0 sleep mode. Certain peripheral clocks have selectable sources these are controlled by the CLK_CLKSEL1 &...
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ISD91200 Series Technical Reference Manual enters DPD mode with insufficient time to allow an ICE tool to activate the SWD debug port. Especially during development it is recommended that some checks are placed in the boot sequence to prevent device going to power down. A register bit, CLK_DBGPD.DISPDREQ is included for this purpose that will disable power down features.
ISD91200 Series Technical Reference Manual 5.3.4.4 Level3: Deep Sleep mode. The Deep Sleep mode is the lowest power state where the Cortex-M0 and all logic state are preserved. In Deep Sleep mode the HIRC oscillator is shut down and a low speed oscillator is selected, if LXT is active this source is selected, if not then LIRC is enabled and selected.
ISD91200 Series Technical Reference Manual 5.3.6 Register Description System Power Control Register (CLK_PWRCTL) This is a protected register, to write to register, first issue the unlock sequence. Register Offset Description Reset Value CLK_PWRCTL CLK_BA + 0x00 System Power Control Register 0xXX00_000D Table 5-36 System Power Control Register (CLK_PWRCTL, address 0x5000_0200)...
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ISD91200 Series Technical Reference Manual Flash ROM Control Enable/Disable Bit [19]: for Stop mode operation Bit [18]: for Sleep mode operation [19:18] FLASHEN 1: Turn off flash 0: Normal Note: It takes 10us to turn on the flash to normal OSC10k Enabled Control Determines whether OSC10k is enabled in DPD mode.
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ISD91200 Series Technical Reference Manual AHB Device Clock Enable Control Register (CLK_AHBCLK) These register bits are used to enable/disable the clock source for AHB (Advanced High-Performance Bus) blocks. This is a protected register, to write to register, first issue the unlock sequence...
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ISD91200 Series Technical Reference Manual APB Device Clock Enable Control Register (CLK_APBCLK0) These register bits are used to enable/disable clocks for APB (Advanced Peripheral Bus) peripherals. To enable the clocks write ‘1’ to the appropriate bit. To reduce power consumption and disable the peripheral, write ‘0’...
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ISD91200 Series Technical Reference Manual BIQ and ALC Clock Enable Control [18] BIQALCKEN 0=Disable. 1=Enable. SAR Analog-digital-converter (ADC) Clock Enable Control [17] SARADCKEN 0=Disable. 1=Enable. UART0 Clock Enable Control [16] UART0CKEN 0=Disable. 1=Enable. UART1 Clock Enable Control [15] UART1CKEN 0=Disable.
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ISD91200 Series Technical Reference Manual DPD State Register (CLK_DPDSTATE) The Deep Power Down State register is a user settable register that is preserved during Deep Power Down (DPD). Software can use this register to store a single byte during a DPD event. The DPDSTSRD register reads back the current state of the CLK_DPDSTATE register.
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ISD91200 Series Technical Reference Manual Clock Source Select Control Register 1(CLK_CLKSEL1) Clock multiplexors are a glitch free design to ensure smooth transitions between asynchronous clock sources. As such, both the current clock source and the target clock source must be enabled for switching to occur.
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ISD91200 Series Technical Reference Manual TIMER1 Clock Source Select 000 = clock source from LIRC. 001 = clock source from LXT. [14:12] TMR1SEL 010 = clock source from HXT. 011 = clock source from external pin (GPIOA[11]). 1xx = clock source from HCLK.(default)
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ISD91200 Series Technical Reference Manual Clock Source Select Control Register 2(CLK_CLKSEL2) Before changing clock source, ensure that related clock sources (pre-select and new-select) are enabled. Register Offset Description Reset Value CLK_CLKSEL2 CLK_BA + 0x1C R/W Clock Source Select Control Register 2...
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ISD91200 Series Technical Reference Manual Sleep Clock Enable Control Register (CLK_SLEEPCTL) These register bits are used to enable/disable clocks during sleep mode. It works in conjunction with CLK_AHBCLK and CLK_APBCLK0 clock register to determine whether a clock source remains active during CPU Sleep mode.
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ISD91200 Series Technical Reference Manual [19] Reserved BIQ and ALCSleep Clock Enable Control [18] BIQALCKEN 0=Disable. 1=Enable. SARADC Sleep Clock Enable Control [17] SARADCCKEN 0=Disable. 1=Enable. UART0 Sleep Clock Enable Control [16] UART0CKEN 0=Disable. 1=Enable. UART1 Sleep Clock Enable Control 0=Disable.
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ISD91200 Series Technical Reference Manual PDMA Controller Sleep Clock Enable Control PDMACKEN 0=Disable. 1=Enable. CPU Clock Sleep Enable (HCLK) Must be left as ‘1’ for normal operation. HCLKCKEN 0=Disable. 1=Enable. Release Date: Sep 16, 2019 - 129 - Revision 2.4...
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ISD91200 Series Technical Reference Manual Power State Flag Register (CLK_PWRSTSF) Register Offset Description Reset Value CLK_PWRSTSF CLK_BA + 0x24 Power State Flag Register 0x0000_0000 Reserved SPDF STOPF Table 5-46 Power State Flag Register (CLK_PWRSTSF, address 0x5000_0224) Bit Description. Bits Description...
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ISD91200 Series Technical Reference Manual Debug Power Down Register (CLK_DBGPD) Register Offset Description Reset Value CLK_DBGPD CLK_BA + 0x28 Debug Port Power Down Disable Register 0x0000_00XX ICEDATST ICECLKST Reserved DISPDREQ Table 5-47 Debug Power Down Register (CLK_DBGPD, address 0x5000_0228) Bit Description.
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ISD91200 Series Technical Reference Manual Deep Power Down 10K Wakeup Timer (CLK_WAKE10K) Register Offset Description Reset Value CLK_WAKE10K CLK_BA + 0x2C R/W Deep Power Down 10K Wakeup Timer 0x0000_0001 WAKE10KEN Reserved WKTMRSTS WKTMRSTS Reserved SELWKTMR SELWKTMR Table 5-48 Deep Power Down 10K Wakeup Timer (CLK_WAKE10K, address 0x5000_022C) Bit Description.
ISD91200 Series Technical Reference Manual General Purpose I/O 5.4.1 Overview and Features Up to 32 General Purpose I/O pins are available on the I91200 series. These are shared peripheral special function pins under control of the alternate configuration registers. These 32 pins are arranged in 2 ports named with GPIOA, and GPIOB.
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ISD91200 Series Technical Reference Manual 5.4.2.3 Open-Drain Mode For Px_MODEn = 10b the GPIOx port [n] pin is in Open-Drain mode. The GPIO pin supports a digital output function but only with sink current capability, an additional pull-up resister is needed for defining a high state.
ISD91200 Series Technical Reference Manual 5.4.4 Register Description GPIO Port [A/B] I/O Mode Control (Px_MODE) Register Offset Description Reset Value PA_MODE GPIO_BA+0x000 R/W GPIO Port A Pin I/O Mode Control 0xFFFF_FFFF PB_MODE GPIO_BA+0x040 R/W GPIO Port B Pin I/O Mode Control...
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ISD91200 Series Technical Reference Manual GPIO Port [A/B] Input Disable (Px_DINOFF) Register Offset Description Reset Value PA_DINOFF GPIO_BA+0x004 R/W GPIO Port A Pin Input Disable 0x0000_0000 PB_DINOFF GPIO_BA+0x044 R/W GPIO Port B Pin Input Disable 0x0000_0000 Table 5-50 GPIO Input Disable Register...
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ISD91200 Series Technical Reference Manual GPIO Port [A/B] Data Output Value (Px_DOUT) Register Offset Description Reset Value PA_DOUT GPIO_BA+0x008 R/W GPIO Port A Data Output Value 0x0000_FFFF PB_DOUT GPIO_BA+0x048 R/W GPIO Port B Data Output Value 0x0000_FFFF Table 5-51 GPIO Data Output Register (Px_DOUT)
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ISD91200 Series Technical Reference Manual GPIO Port [A/B] Data Output Write Mask (Px _DATMSK) Register Offset Description Reset Value PA_DATMSK GPIO_BA+0x00C R/W GPIO Port A Data Output Write Mask 0xXXXX_0000 PB_DATMSK GPIO_BA+0x04C R/W GPIO Port B Data Output Write Mask...
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ISD91200 Series Technical Reference Manual GPIO Port [A/B] Pin Value (Px _PIN) Register Offset Description Reset Value PA_PIN GPIO_BA+0x010 R GPIO Port A Pin Value 0x0000_XXXX PB_PIN GPIO_BA+0x050 R GPIO Port B Pin Value 0x0000_XXXX Table 5-53 GPIO PIN Value Register (Px_PIN)
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ISD91200 Series Technical Reference Manual GPIO Port [A/B] De-bounce Enable (Px _DBEN) Register Offset Description Reset Value PA_DBEN GPIO_BA+0x014 R/W GPIO Port A De-bounce Enable 0xXXXX_0000 PB_DBEN GPIO_BA+0x054 R/W GPIO Port B De-bounce Enable 0xXXXX_0000 Table 5-54 GPIO Debounce Enable Register (Px_DBEN)
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ISD91200 Series Technical Reference Manual GPIO Port [A/B] Interrupt Mode Control (Px _INTTYPE) Register Offset Description Reset Value PA_INTTYPE GPIO_BA+0x018 R/W GPIO Port A Interrupt Trigger Type 0xXXXX_0000 PB_INTTYPE GPIO_BA+0x058 R/W GPIO Port B Interrupt Trigger Type 0xXXXX_0000 Table 5-55 GPIO Interrupt Mode Control (Px_INTTYPE)
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ISD91200 Series Technical Reference Manual GPIO Port [A/B] Interrupt Enable Control (Px _INTEN) Register Offset Description Reset Value PA_INTEN GPIO_BA+0x01C R/W GPIO Port A Interrupt Enable 0x0000_0000 PB_INTEN GPIO_BA+0x05C R/W GPIO Port B Interrupt Enable 0x0000_0000 Table 5-56 GPIO Interrupt Enable Control Register (Px_INTEN)
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ISD91200 Series Technical Reference Manual GPIO Port [A/B] Interrupt Source Flag(Px _INTSRC) Register Offset Description Reset Value PA_INTSRC GPIO_BA+0x020 R/W GPIO Port A Interrupt Source Flag 0x0000_0000 PB_INTSRC GPIO_BA+0x060 R/W GPIO Port B Interrupt Source Flag 0x0000_0000 Table 5-57 GPIO Interrupt Source Flag Register (Px_INTSRC)
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ISD91200 Series Technical Reference Manual Interrupt De-bounce Control (GPIO_DBCTL ) Register Offset Description Reset Value DBCTL GPIO_BA+0x180 R/W Interrupt De-bounce Control 0x0000_0020 Table 5-58 GPIO Interrupt De-bounce Control Register (GPIO_DBCTL ) Reserved ICLKON DBCLKSRC DBCLKSEL Bits Description [31:6] Reserved Reserved.
ISD91200 Series Technical Reference Manual Brownout Detection and Temperature Alarm The I91200 is equipped with a Brown-Out voltage detector. The Brown-Out detector features a configurable trigger level and can be configured by flash to be active upon reset. The Brown-Out detector also has a power saving mode where detection can be set up to be active for a configurable on and off time.
ISD91200 Series Technical Reference Manual 5.5.2 Brownout Register Description This register is initialized by user flash configuration bits config0[22:18]. Brown-Out Detector Select Register (BOD_BODSEL) Register Offset Description Reset Value BOD_BODSEL BOD_BA+0x00 Brown Out Detector Select Register 0x0000_0000 Table 5-59 Brownout Detector Select Register (BOD_BODSEL, address 0x4008_4000)
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ISD91200 Series Technical Reference Manual Brown-Out Detector Enable Register (BOD_BODCTL) This register is initialized by user flash configuration bit config0[23]. If config0[23]=1, then reset value of is 0x7. The effect of this is to generate a NMI interrupt (default NMI interrupt is BOD BOD_BODCTL interrupt) if BOD circuit detects a voltage below 2.1V.
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ISD91200 Series Technical Reference Manual BOD Interrupt Enable BODINTEN 0= Disable BOD Interrupt. 1= Enable BOD Interrupt. BOD Enable 1xb = Enable continuous BOD detection. [1:0] BODEN 01b = Enable time multiplexed BOD detection. See BOD_BODDTMR register. 00b = Disable BOD Detection.
ISD91200 Series Technical Reference Manual Detection Time Multiplex Register (BOD_BODDTMR) The BOD detector can be set up to take periodic samples of the supply voltage to minimize power consumption. The circuit can be configured and used in Standby Power Down (SPD) mode and can wake up the device if a BOD is event detected.
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ISD91200 Series Technical Reference Manual Re pe a te d S TOP S TART S TOP S TART S DA LO W S CL HIG H HD;S TA S U;S TA S U;S TO HD;DAT S U;DAT Figure 5-9 I2C Bus Timing The device’s on-chip I2C logic provides the serial interface that meets the I2C bus standard mode...
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ISD91200 Series Technical Reference Manual 3 - 7 NACK A4 - A1 D5 - D1 Figure 5-10 I2C Protocol 5.6.1.2 Data transfer on the I2C-bus A master-transmitter always begins by addressing a slave receiver with a 7-bit address. For a transaction where the master-transmitter is sending data to the slave, the transfer direction is not changed, master is always transmitting and slave acknowledges the data.
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ISD91200 Series Technical Reference Manual START condition STOP condition Figure 5-13 START and STOP condition 5.6.1.4 Slave Address Transfer The first byte of data transferred by the master immediately after the START signal is the slave address. This is a 7-bits calling address followed by a RW bit. The RW bit signals the slave the data transfer direction.
ISD91200 Series Technical Reference Manual clock pulse for acknowledgement SCL FROM MASTER DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge START condition Figure 5-15 Acknowledge on the I2C bus 5.6.2 Modes of Operation The on-chip I2C ports support five operation modes, Master transmitter, Master receiver, Slave transmitter, Slave receiver, and GC call.
ISD91200 Series Technical Reference Manual 5.6.3 Data Transfer Flow in Five Operating Modes The five operating modes are: Master/Transmitter, Master/Receiver, Slave/Transmitter, Slave/Receiver and GC Call. Bits STA, STO and AA in I2C_CTL register will determine the next state of the SIO hardware after SI flag is cleared.
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ISD91200 Series Technical Reference Manual Set STA to generate a START. From Slave Mode (C) A START has been transmitted. (STA,STO,SI,AA)=(0,0,1,X) SLA+W will be transmitted; ACK bit will be received. From Master/Receiver (B) SLA+W will be transmitted; ACK bit will be received.
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ISD91200 Series Technical Reference Manual Set STA to generate a START. From Slave Mode (C) A START has been transmitted. (STA,STO,SI,AA)=(0,0,1,X) SLA+R will be transmitted; ACK bit will be received. From Master/Transmitter (A) SLA+R has been transmitted; SLA+R has been transmitted;...
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ISD91200 Series Technical Reference Manual Set AA Own SLA+R has been received; ACK has been return. Arbitration lost SLA+R/W as master; Own SLA+R has been received; ACK has been return. (STA,STO,SI,AA)=(0,0,1,0) (STA,STO,SI,AA)=(0,0,1,1) Last data byte will be transmitted; Data byte will be transmitted;...
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ISD91200 Series Technical Reference Manual Set AA Own SLA+W has been received; ACK has been return. Arbitration lost SLA+R/W as master; Own SLA+W has been received; ACK has been return. (STA,STO,SI,AA)=(0,0,1,0) (STA,STO,SI,AA)=(0,0,1,1) Data byte will be received; Data byte will be received;...
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ISD91200 Series Technical Reference Manual Set AA Reception of the general call address and one or more data bytes; ACK has been return. Arbitration lost SLA+R/W as master; and address as SLA by general call; ACK has been return. (STA,STO,SI,AA)=(X,0,1,0) (STA,STO,SI,AA)=(X,0,1,1) Data byte will be received;...
ISD91200 Series Technical Reference Manual 5.6.4 I2C Protocol Registers The CPU interfaces to the SIO port through the following thirteen special function registers: I2C_CTL (control register), I2C_STATUS (status register), I2C_DAT (data register), I2C_ADDRn (address registers, n=0~3), I2C_ADDRMSKn (address mask registers, n=0~3), I2C_CLKDIV (clock rate register) and I2C_TOCTL (Time-out counter register).
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ISD91200 Series Technical Reference Manual I2C Data Register: DATA.7 DATA.6 DATA.5 DATA.4 DATA.3 DATA.2 DATA.1 DATA.0 shifting direction Figure 5-22 I2C Data Shift Direction 5.6.4.3 Control Register (I2C_CTL) The CPU can read from and write to this 8-bit field of I2C_CTL[7:0]. Two bits are affected by hardware: the SI bit is set when the I2C hardware requests a serial interrupt, and the STO bit is cleared when a STOP condition is present on the bus.
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ISD91200 Series Technical Reference Manual with any clock frequency up to 1M Hz from master I2C device. Data Baud Rate of I2C = PCLK /(4x(I2C_CLKDIV[7:0]+1)). If PCLK=16MHz, the I2C_CLKDIV[7:0] = 40 (28H), data baud rate of I2C = 16MHz/(4x(40 +1)) = 97.5Kbits/sec.
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ISD91200 Series Technical Reference Manual I2C DATA REGISTER (I2C_DAT) Register Offset Description Reset Value I2C_DAT I2C_BA+0x08 I2C DATA Register 0x0000_0000 DAT[7:0] Bits Description [31:8] Reserved Reserved. I2C Data Register During master or slave transmit mode, data to be transmitted is written to this [7:0] register.
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ISD91200 Series Technical Reference Manual I2C STATUS REGISTER (I2C_STATUS ) Register Offset Description Reset Value I2C_STATUS I2C_BA+0x0C I2C Status Register 0x0000_00F8 STATUS[7:0] Bits Description [31:8] Reserved Reserved. I2C Status Register The status register of I2C: The three least significant bits are always 0. The five most significant bits contain the status code.
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ISD91200 Series Technical Reference Manual I2C DATA BAUD RATE CONTROL REGISTER (I2C_CLKDIV) Register Offset Description Reset Value I2C_CLKDIV I2C_BA+0x10 I2C clock divided Register 0x0000_0000 DIVIDER[7:0] Bits Description [31:8] Reserved Reserved. I2C Clock Divided Register [7:0] DIVIDER The I2C clock rate bits: Data Baud Rate of I2C = PCLK /(4x(I2C_CLKDIV+1)).
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ISD91200 Series Technical Reference Manual I2C TIME-OUT COUNTER REGISTER (I2C_TOCTL) Register Offset Description Reset Value I2C_TOCTL I2C_BA+0x14 I2C Time out control Register 0x0000_0000 Reserved TOCEN TOCDIV4 TOIF Bits Description [31:3] Reserved Reserved. Time-out Counter Control Bit 0 = Disable. TOCEN 1 = Enable.
ISD91200 Series Technical Reference Manual PWM Generator and Capture Timer 5.7.1 Introduction The I91200 has two PWM generators which can be configured as 4 independent PWM outputs, PWM0CH0, PWM0CH1, PWM0CH2 and PWM0CH3, or as a complementary PWM pairs with programmable dead-zone generator. Each PWM Generator has an 8-bit pre-scaler, a clock divider...
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ISD91200 Series Technical Reference Manual 5.7.2.2 Capture Function Features: Timing control logic shared with PWM Generators. 2 Capture input channels shared with 2 PWM output channels. Each channel supports a rising latch register (RCAPDAT), a falling latch register...
ISD91200 Series Technical Reference Manual 5.7.3 PWM Generator Architecture The following figures illustrate the architecture of the PWM. PWM0CH01SEL(CLK_CLKSEL1[29:28]) PWM0CH01EN(CLK_APBCLK0[20]) PWM0CH01_CLK CLK48M HCLK CLK32K CLK10K Figure 5-24 PWM Generator Clock Source Control DZI01 Dead Zone Generator 0 CSR0(CSR[2:0]) CNR0, CMR0, PWM- PA.12/PWM0...
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ISD91200 Series Technical Reference Manual CMP < PERIOD: PWM low width= (PERIOD-CMP) unit ; PWM high width=(CMP+1) unit. CMP = 0: PWM low width = (PERIOD) unit; PWM high width=1 unit Note: 1. Unit = one PWM clock cycle.
ISD91200 Series Technical Reference Manual 5.7.5 PWM Double Buffering, Auto-reload and One-shot Operation The I91200 series PWM Timers are double buffered, the reload value is updated at the start of next period without affecting current timer operation. The PWM counter reset value can be written into PWM_PERIOD0~1 and current PWM counter value can be read from PWM_CNT0~1.
ISD91200 Series Technical Reference Manual 5.7.7 Dead-Zone Generator The I91200 PWM generator includes a Dead Zone generator. This is used to ensure neither PWM output is active simultaneously for power device protection. The function generates a programmable time gap between rising PWM outputs. The user can program PPRx.DZI to determine the Dead Zone interval.
ISD91200 Series Technical Reference Manual 5.7.8 Capture Timer Operation Instead of using the PWM generator to output a modulated signal, it can be configured as a capture timer to measure a modulated input. Capture channel 0 and PWM0CH0 share one timer and Capture channel 1 and PWM0CH1 share another timer.
ISD91200 Series Technical Reference Manual 5.7.9 PWM-Timer Interrupt Architecture There are two PWM interrupts, PWM0_INT, PWM1_INT, which are multiplexed into PWM0_IRQ. PWM 0 and Capture 0 share one interrupt, PWM1 and Capture 1 share the same interrupt. Figure 5-32 PWM- Timer Interrupt Architecture Diagram demonstrates the architecture of PWM-Timer interrupts.
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ISD91200 Series Technical Reference Manual [15:12] Reserved Reserved. PWM-timer 1 Auto-reload/One-shot Mode 0 = One-Shot Mode. [11] CNTMODE1 1 = Auto-load Mode. Note: A rising transition of this bit will cause PWM_PERIOD1 and PWM_CMPDAT1 to be cleared. PWM-timer 1 Output Inverter ON/OFF...
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ISD91200 Series Technical Reference Manual PWM Data Register 1-0 (PWM_CNT) Register Offset Description Reset Value PWM_CNT0 PWM_BA+0x014 R PWM Data Register 0 0x0000_0000 PWM_CNT1 PWM_BA+0x020 R PWM Data Register 1 0x0000_0000 PWM_CNT2 PWM_BA+0x02C R PWM Data Register 2 0x0000_0000 PWM_CNT3...
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ISD91200 Series Technical Reference Manual PWM Interrupt Flag Register (PWM_INTSTS) Register Offset Description Reset Value PWM_INTSTS PWM_BA+0x044 R/W PWM Interrupt Flag Register 0x0000_0000 Reserved PIF3 PIF2 PIF1 PIF0 Table 5-69 PWM Interrupt Flag Register (PWM_INTSTS, address 0x4004_0044). Bits Description [31:4] Reserved Reserved.
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ISD91200 Series Technical Reference Manual Capture Control Register (PWM_CAPCTL01) Register Offset Description Reset Value PWM_CAPCTL01 PWM_BA+0x050 R/W Capture Control Register For Pair Of PWM0CH0 And 0x0000_0000 PWM0CH1 Reserved CFLIF1 CRLIF1 Reserved CAPIF1 CAPEN1 CFLIEN1 CRLIEN1 CAPINV1 Reserved CFLIF0 CRLIF0 Reserved...
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ISD91200 Series Technical Reference Manual Channel 1 Inverter ON/OFF [16] CAPINV1 0 = Inverter OFF. 1 = Inverter ON. Reverse the input signal from GPIO before Capture timer [15:8] Reserved Reserved. PWM_FCAPDAT0 Latched Indicator Bit When input channel 0 has a falling transition, PWM_FCAPDAT0 was latched with...
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ISD91200 Series Technical Reference Manual Capture Control Register (PWM_CAPCTL23) Register Offset Description Reset Value PWM_CAPCTL23 PWM_BA+0x054 R/W Capture Control Register For Pair Of PWM0CH2 And 0x0000_0000 PWM0CH3 Reserved CFLIF3 CRLIF3 Reserved CAPIF3 CAPEN3 CFLIEN3 CRLIEN3 CAPINV3 Reserved CFLIF2 CRLIF2 Reserved...
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ISD91200 Series Technical Reference Manual Channel 3 Rising Latch Interrupt Enable 0 = Disable rising edge latch interrupt. [17] CRLIEN3 1 = Enable rising edge latch interrupt. When enabled, capture block generates an interrupt on rising edge of input. Channel 3 Inverter ON/OFF...
ISD91200 Series Technical Reference Manual Real Time Clock (RTC) Overview Real Time Clock (RTC) unit provides real time clock, calendar and alarm functions. The clock source of the RTC is an external 32.768 kHz crystal connected at pins XI32K and XO32K or from an external 32.768 kHz oscillator output fed to pin XI32K.
ISD91200 Series Technical Reference Manual 5.8.2 RTC Block Diagram Time Alarm Calendar Alarm ALMIEN(INTEN[0]) Register (TAR) Register (CAR) ALMIF(INTSTS[0]) Alarm Compare Interrupt Operation Time Load Calendar Load Register (TLR) Register (CLR) Wakeup CPU from Power-down mode (sec) 1/128 change Leap Year Indicator (LIP)
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ISD91200 Series Technical Reference Manual Table 5-76 RTC Frequency Compensation Example Example 1: Frequency Counter Measurement : 32773.65Hz ( > 32768 Hz) Integer Part: 32773 = 0x8005 RTC_FREQADJ. INTEGER= (32773 – 32761) = 12 = 0x0C Fractional Part: 0.65 X 60 = 39 = 0x27 RTC_FREQADJ.
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ISD91200 Series Technical Reference Manual RTC_TALM 00:00:00 (hour : minute : second) RTC_CLKFMT 1 (24 hr. mode) RTC_WEEKDAY 6 (Saturday) RTC_INTEN RTC_INTSTS RTC_LEAPYEAR RTC_TICK PWRTOUT 5555 4. In RTC_TIME and RTC_TALM, only 2 BCD digits are used to express “year”. It is assumed that 2 BCD digits of xY denote 20xY, but not 19xY or 21xY.
ISD91200 Series Technical Reference Manual 5.8.4 Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Offset Description Reset Value RTC Base Address: RTC_BA = 0x4000_8000 RTC_INIT RTC_BA+0x000 RTC Initialization Register...
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ISD91200 Series Technical Reference Manual RTC Frequency Compensation Register (RTC_FREQADJ) Register Offset Description Reset Value RTC_BA+0x008 R/W RTC_FREQADJ RTC Frequency Compensation Register 0x0000_0700 Reserved Reserved Reserved INTEGER Reserved FRACTION Table 5-80 RTC Frequency Compensation Register (RTC_FREQADJ, address 0x4000_8008). Bits Description...
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ISD91200 Series Technical Reference Manual RTC Time Load Register (RTC_TIME) This register is Read Only until access enable password is written to RTC_RWEN register. The register returns the current time. Register Offset Description Reset Value RTC_BA+0x00C R/W RTC_TIME Time Load Register...
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ISD91200 Series Technical Reference Manual RTC Calendar Load Register (RTC_CAL) This register is Read Only until access enable password is written to RTC_RWEN register. The register returns the current date. Register Offset Description Reset Value RTC_BA+0x010 R/W RTC_CAL Calendar Load Register...
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ISD91200 Series Technical Reference Manual RTC Time Scale Selection Register (RTC_CLKFMT) Register Offset Description Reset Value RTC_BA+0x014 R/W RTC_CLKFMT Time Scale Selection Register 0x0000_0001 Table 5-83 RTC Time Scale Selection Register (RTC_CLKFMT, address 0x4000_8014). Reserved 24HEN Bits Description [31:1] Reserved Reserved.
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ISD91200 Series Technical Reference Manual RTC Day of the Week Register (RTC_WEEKDAY) Register Offset Description Reset Value RTC_BA+0x018 R/W RTC_WEEKDAY Day of the Week Register 0x0000_0000 Reserved WEEKDAY Table 5-84 RTC Day of Week Register (RTC_WEEKDAY, address 0x4000_8018). Bits Description...
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ISD91200 Series Technical Reference Manual RTC Time Alarm Register (RTC_TALM) Register Offset Description Reset Value RTC_BA+0x01C R/W RTC_TALM Time Alarm Register 0x0000_0000 Reserved Reserved TENHR Reserved TENMIN Reserved TENSEC Table 5-85 RTC Time Alarm Register (RTC_TALM, address 0x4000_801C). Bits Description...
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ISD91200 Series Technical Reference Manual RTC Time-Tick Register (RTC_TICK) Register Offset Description Reset Value RTC_BA+0x030 R/W RTC_TICK RTC Time Tick Register 0x0000_0000 Reserved TWKEN TICKSEL Table 5-90 RTC Time-Tick Register (RTC_TICK, address 0x4000_8030). Bits Description [31:4] Reserved Reserved. RTC Timer Wakeup CPU Function Enable Bit If TWKE is set before CPU is in power-down mode, when a RTC Time-Tick or Alarm Match occurs, CPU will wake up.
ISD91200 Series Technical Reference Manual Serial 0 Peripheral Interface (SPI0) Controller 5.9.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which operates in full duplex mode. Devices communicate in master/slave mode with 4-wire bi-directional interface. The I91200 series contains an SPI controller performing a serial-to-parallel conversion of data received from an external device, and a parallel-to-serial conversion of data transmitted to an external device.
ISD91200 Series Technical Reference Manual 5.9.4 SPI0 Function Descriptions 5.9.4.1 SPI Engine Clock and SPI Serial Clock The SPI controller derives its clock source from the system HCLK as determined by the CLKSEL1 register. The frequency of the SPI master clock is determined by the divisor ratio SPI0_CLKDIV.
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ISD91200 Series Technical Reference Manual 5.9.4.3 Slave Select In master mode, the SPI controller can address up to two off-chip slave devices through the slave select output pins SPI0_SSB0 and SPI0_SSB1. Only one slave can be addressed at any one time. If more slave address lines are required, GPIO pins can be manually configured to provide additional SSB lines.
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ISD91200 Series Technical Reference Manual edge of serial clock SPI0_SCLK. If RXNEG=1 then data is clocked in on the falling edge of SPI0_SCLK. If RXNEG=0 data is clocked in on the rising edge of SPI0_SCLK. Note that RXNEG should be the inverse of TXNEG for standard SPI operation.
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ISD91200 Series Technical Reference Manual transmission out the SPI port. The CortexM0 stores data in a little endian format; that is the LSB of a multi-byte word or half-word are stored first in memory. Consider how the CortexM0 stores the following arrays in memory: 1.
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ISD91200 Series Technical Reference Manual 2. If the slave select active but there is no any serial clock input, the SLVBEIF also active when the slave select goes to inactive state. Slave Under-run and Slave Error 1 interrupts In Slave mode, if there is no any data is written to the SPI0_TX register, the under-run event, TXUFIF (SPI0_STATUS[19]) will active when the slave select active and the serial clock input this controller.
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ISD91200 Series Technical Reference Manual SPI0_MOSI0 and SPI0_MOSI1 pin, same as Master mode. SPICLKx SCLK MISOx[0] MISOx[1:0] MISO Slave 0 MOSIx[0] MOSIx[1:0] MOSI SPI Controller Master SPISSx0 SPISSx1 SCLK MISOx[1] MISO Slave 1 MOSIx[1] MOSI Figure 5-41 2-Bit Mode System Architecture...
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ISD91200 Series Technical Reference Manual I/O transfer. The QDIODIR bit (SPI0_CTL[20]) is used to define the direction of the transfer data. When the QDIODIR bit is set to 1, the controller will send the data to external device. When the QDIODIR bit is set to 0, the controller will read the data from the external device.
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ISD91200 Series Technical Reference Manual SPI0_MISO1, SPI0_MOSI0 and SPI0_MOSI1 will be set as data input ports. SPICLKx SCLK MISOx[1] MISOx[0] MISOx[1:0] HOLDB MISO Quad SpiFlash MOSIx[0] MOSIx[1:0] MOSI SPI Controller MOSIx[1] Master SPISSx0 SPISSx1 Figure 5-45 Quad Mode System Architecture...
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ISD91200 Series Technical Reference Manual transmission logic unit draws out the last datum of the transmit FIFO buffer, so that the 4-level transmit FIFO buffer is empty, the TXEMPTY bit will be set to 1. Notice that the TXEMPTY flag is set to 1 while the last transaction is still in progress.
ISD91200 Series Technical Reference Manual transmission will start when the slave device receives clock signal from master. Data can be written to SPI0_TX register as long as the TXFULL flag is 0. After all data have been drawn out by the SPI transmission logic unit and the SPI0_TX register is not updated by software, the TXEMPTY flag will be set to 1.
ISD91200 Series Technical Reference Manual 5.9.6 SPI Configuration Examples Example 1, SPI controller is set as a master to access an off-chip slave device with following specifications: Data bit latched on positive edge of serial clock Data bit driven on negative edge of serial clock ...
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ISD91200 Series Technical Reference Manual To configure the SPI interface to the above specifications perform the following steps: 1) Configure the SPI0_SSCTL register. SPI0_SSCTL.SSACTPOL=1 for active high slave select, SPI0_SSCTL.SS_LTRIG=1 for level sensitive trigger. 2) Configure SPI0_CTL register. SPI0_CTL.SLAVE=1 slave mode, SPI0_CTL.CLKPOL=1 for SCLK polarity idle high, set SPI0_CTL.TXNEG=1 so that data changes...
ISD91200 Series Technical Reference Manual 5.9.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SPI Base Address: SPI0_BA = 0x4003_0000 SPI0_CTL SPI0_BA + 0x00 Control and Status Register 0x0000_0034 SPI0_CLKDIV...
ISD91200 Series Technical Reference Manual 5.9.8 Register Description SPI Control and Status Register (SPI0_CTL) Register Offset Description Reset Value SPI0_CTL SPI0_BA + 0x00 R/W Control and Status Register 0x0000_0034 Reserved RXMODEEN RXTCNTEN QUADIOEN DUALIOEN QDIODIR REORDER SLAVE UNITIEN TWOBIT Reserved...
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ISD91200 Series Technical Reference Manual Byte Reorder Function Enable 0 = Byte reorder function Disabled. 1 = Byte reorder function Enabled. A byte suspend interval will be inserted between each byte. The period of the byte suspend interval depends on the setting of SUSPITV.
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ISD91200 Series Technical Reference Manual Suspend Interval (Master Only) The four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
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ISD91200 Series Technical Reference Manual 0 = Slave mode time-out interrupt Disabled. 1 = Slave mode time-out interrupt Enabled. Slave 3-wire Mode Enable This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface consisting of SPI0_CLK, SPI0_MISO, and SPI0_MOSI.
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ISD91200 Series Technical Reference Manual SPI DMA Control Register (SPI0_PDMACTL) Register Offset R/W Description Reset Value SPI0_PDMACT SPI0_BA + 0x0C SPI PDMA Control Register 0x0000_0000 Table 5-94 SPI0_PDMACTL Control Register (address SPI0_BA + 0x0C) Reserved PDMARST RXPDMAEN TXPDMAEN Bits Description...
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ISD91200 Series Technical Reference Manual SPI Status Register (SPI0_STATUS) Register Offset R/W Description Reset Value SPI0_STATU SPI0_BA + 0x14 R/W Status Register 0x0005_0110 Table 5-96 SPI Status Register SPI0_STATUS (address SPI0_BA + 0x14) TXCNT RXCNT TXRXRST Reserved TXUFIF TXTHIF TXFULL...
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ISD91200 Series Technical Reference Manual SPI Enable Bit Status (Read Only) 0 = Indicate the transmit control bit is disabled. 1 = Indicate the transfer control bit is active. [15] SPIENSTS Note: The clock source of SPI controller logic is engine clock, it is asynchronous with the system clock.
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ISD91200 Series Technical Reference Manual Slave Select Line Bus Status (Read Only) 0 = Indicates the slave select line bus status is 0. SSLINE 1 = Indicates the slave select line bus status is 1. Note: If SPI0_SSCTL.SSACTPOL is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
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ISD91200 Series Technical Reference Manual SPI Data Transmit Register (SPI0_TX) Register Offset Description Reset Value SPI0_TX SPI0_BA + 0x20 FIFO Data Transmit Register 0x0000_0000 Table 5-99 SPI Data Transmit Register (SPI0_TX, address SPIx_BA + 0x20) Bits Description Data Transmit Register A write to the data transmit register pushes data onto into the 8-level transmit FIFO buffer.
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ISD91200 Series Technical Reference Manual SPI Data Receive Register (SPI0_RX) Register Offset Description Reset Value SPI0_RX SPI0_BA + 0x30 FIFO Data Receive Register 0x0000_0000 Table 5-100 SPI Data Receive Register (SPI0_RX, address SPIx_BA + 30) Bits Description Data Receive Register [31:0] A read from this register pops data from the 8-level receive FIFO.
ISD91200 Series Technical Reference Manual 5.10 Serial 1 Peripheral Interface (SPI1) Controller 5.10.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which operates in full duplex mode. Devices communicate in master/slave mode with 4-wire bi-directional interface.
ISD91200 Series Technical Reference Manual 5.10.4 SPI1 Function Descriptions 5.10.4.1 SPI Engine Clock and SPI Serial Clock The SPI controller derives its clock source from the system HCLK as determined by the CLKSEL1 register. The frequency of the SPI master clock is determined by the divisor ratio SPI1_CLKDIV.
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ISD91200 Series Technical Reference Manual SCLK SCLK MISO MISO Master I91200 MOSI MOSI SPI1 Controller Slave Figure 5-54 SPI1 Slave Mode Application Block Diagram 5.10.4.3 Slave Select In master mode, the SPI controller can address up to one off-chip slave devices through the slave select output pins SPI1_SSB.
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ISD91200 Series Technical Reference Manual 5.10.4.13 Byte Endian APB access to the SPI controller is via the 32bit wide TX and RX registers. When the transfer is set as MSB first (SP1I_CTL.LSB = 0) and the SPI1_CTL.BYTEENDIAN bit is set, the data stored in the TX buffer and RX buffer will be rearranged such that the least significant physical byte is processed first.
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ISD91200 Series Technical Reference Manual It can be seen from Figure 5-58 Byte Order in Memory that byte order for an array of bytes is different than that of an array of words. Now consider if this data were to be sent to the SPI port; the user could: 3.
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ISD91200 Series Technical Reference Manual 5.10.4.15 Interrupt The SPI controller can generate a CPU interrupt when data transfer is finished. When a transfer request triggered by EN is finished, the interrupt flag (SPI_CTL.IF) will be set by hardware. If the SPI interrupt is enabled (SPI1_CTL.IE) this will also generate a CPU interrupt.
ISD91200 Series Technical Reference Manual determined by setting of SPI1_CLKDIV, if the bit content of VARCLK is ‘1’, the output period for that bit is determined by the SPI1_ CLKDIV.DIV1 register. The following figure shows the timing relationships of serial clock (SCLK), to the VARCLK, the DIV0 and the DIV1 registers. A two-bit combination in the VARCLK defines one clock cycle.
ISD91200 Series Technical Reference Manual 5.10.6 SPI Configuration Examples Example 1, SPI controller is set as a master to access an off-chip slave device with following specifications: Data bit latched on positive edge of serial clock Data bit driven on negative edge of serial clock ...
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ISD91200 Series Technical Reference Manual To configure the SPI interface to the above specifications perform the following steps: 8) Configure the SPI1_ SSCTL register. SPI1_ SSCTL.SSLVL=1 for active high slave select, SPI1_ SSCTL.SSR.SSLTRIG=1 for level sensitive trigger. 9) Configure the SPI1_CTL register. Set SPI1_CTL.SLAVE=1 for slave mode, set SPI1_CTL.CLKP=1 for SCLK polarity idle high, set SPI1_CTL.TXNEG=1 so that data changes on falling edge of SCLK,...
ISD91200 Series Technical Reference Manual 5.10.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SPI1 Base Address: SPI1_BA = 0x4003_8000 SPI1_CTL SPI1_BA + 0x00 Control and Status Register 0x0500_0004 SPI1_CLKDIV...
ISD91200 Series Technical Reference Manual 5.10.8 Register Description SPI Control and Status Register (SPI_CTL) Register Offset Description Reset Value SPI1_CTL SPI1_BA + 0x00 R/W Control and Status Register 0x0500_0004 Reserved DMABURST TXFULL TXEMPTY RXFULL RXEMPTY VARCLKEN TWOB FIFO BYTEENDIAN BYTESLEEP...
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ISD91200 Series Technical Reference Manual TWOB Two Bits Transfer Mode 1 = Enable two-bit transfer mode. 0 = Disable two-bit transfer mode. [22] Note that when enabled in master mode, MOSI data comes from SPI1_TX0 and MOSI data from SPI1_TX1. Likewise SPI1_RX0 receives bit stream from MISO0 and SPI1_RX1 from MISO1.
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ISD91200 Series Technical Reference Manual LSB First 0 = The MSB is transmitted/received first (which bit in SPI1_TX0/1 and SPI1_RX0/1 register that is depends on the TXBITLEN field). [10] 1 = The LSB is sent first on the line (bit 0 of SPI1_TX0/1), and the first bit received from the line will be put in the LSB position in the Rx register (bit 0 of SPI1_RX0/1).
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ISD91200 Series Technical Reference Manual TXBITLEN Transmit Bit Length This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted. 00001 = 1 bit 00010 = 2 bit 00011 = 3 bit 00100 = 4 bit...
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ISD91200 Series Technical Reference Manual RXNEG Receive At Negative Edge 0 = The received data input signal is latched at the rising edge of SCLK. 1 = The received data input signal is latched at the falling edge of SCLK.
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ISD91200 Series Technical Reference Manual Clock Divider Register (master only) [15:0] CLKDIV0 The value in this field is the frequency division of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation:...
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ISD91200 Series Technical Reference Manual Slave Select Level Trigger (Slave only) 0 = The input slave select signal is edge-trigger. This is the default value. SSLTRIG 1 = The slave select signal will be level-trigger. It depends on SSLVL to decide the signal is active low or active high.
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ISD91200 Series Technical Reference Manual Table 5-104 SPI Data Receive Register (SPI1_RX1, address 0x4003_8010) Bits Description Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the [31:0] SPI1_CTL register.
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ISD91200 Series Technical Reference Manual Table 5-106 SPI Data Transmit Register (SPI1_TX0, address 0x4003_8020) Bits Description Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the SPI1_CTL register.
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ISD91200 Series Technical Reference Manual Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the SPI1_CTL register. For example, if TXBITLEN is set to 0x08 and the TXNUM is set to [31:0] 0x0, the bit SPI1_TX0[7:0] will be transmitted in next transfer.
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ISD91200 Series Technical Reference Manual Reserved Reserved Reserved RXMDAEN TXMDAEN Reserved Table 5-109 SPI DMA Control Register (DMA, address 0x4003_8038) Bits Description [31:2] Reserved Reserved Receive DMA Start 1 = Enable RXMDAEN 0 = Disable Set this bit to 1 will start the receive DMA process. SPI module will issue request to DMA module automatically.
ISD91200 Series Technical Reference Manual 5.11 Timer Controller 5.11.1 General Timer Controller The I91200 provides two general 24bit timer modules, TIMER0 and TIMER1. They allow the user to implement event counting or provide timing control for applications. The timer can perform functions such as frequency measurement, event counting, interval measurement, clock generation and delay timing.
ISD91200 Series Technical Reference Manual 5.11.5 Register Description Timer Control Register (TIMERn_CTL) Register Offset Description Reset Value TMRn_CTL TMRn_BA+0x00 R/W Timer Control and Status Register 0x0000_0005 Reserved CNTEN INTEN OPMODE[1:0] RSTCNT ACTSTS Reserved Reserved CNTDATEN Reserved PSC[7:0] Table 5-110 Timer Control and Status Register (TIMERx_CTL, address 0x4001_0000 + x *0x20).
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ISD91200 Series Technical Reference Manual Timer Active Status Bit (Read Only) This bit indicates the counter status of timer. [25] ACTSTS 0 = Timer is not active. 1 = Timer is active. [24:17] Reserved Reserved. Data Latch Enable When CNTDATEN is set, TIMERx_CNT (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting.
ISD91200 Series Technical Reference Manual 5.12 Watchdog Timer The purpose of Watchdog Timer is to perform a system reset if software is not responding as designed. This prevents system from hanging for an infinite period of time. The watchdog timer includes a 18-bit free running counter with programmable time-out intervals.
ISD91200 Series Technical Reference Manual 5.12.2 Register Description Watchdog Timer Control Register (WDT_CTL) This is a protected register, to write to register, first issue the unlock sequence (refer to SYS_REGLCTL). Only flag bits, IF and RSTF are unprotected and can be write-cleared at any time.
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ISD91200 Series Technical Reference Manual Watchdog Timer Reset Flag When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is disabled, then the Watchdog timer RSTF has no effect on this bit.
ISD91200 Series Technical Reference Manual 5.13 UART Interface Controller The I91200 includes a Universal Asynchronous Receiver/Transmitter (UART). The UART supports high speed operation and flow control functions as well as protocols for Serial Infrared (IrDA) and Local interconnect Network (LIN).
ISD91200 Series Technical Reference Manual 5.13.2 Features of UART controller • UART supports 8 byte FIFO for receive and transmit data payloads. • PDMA access support. • Auto flow control function (/CTS, /RTS) supported. • Programmable baud-rate generator. • Fully programmable serial-interface characteristics: 5-, 6-, 7-, or 8-bit character.
ISD91200 Series Technical Reference Manual 5.13.3 Block Diagram The UART clock control and block diagram are shown as following. CLK_APBCLK0->UARTx_EN UARTx_CLK HCLK 1/(UARTDIV+1) CLK_CLKDIV0->UARTDIV Figure 5-71 UART Clock Control Diagram APB BUS Status & control Status & control Control and...
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ISD91200 Series Technical Reference Manual TX_FIFO The transmitter is buffered with an 8 byte FIFO to reduce the number of interrupts presented to the CPU. RX_FIFO The receiver is buffered with an 8 byte FIFO (plus three error bits per byte) to reduce the number of interrupts presented to the CPU.
ISD91200 Series Technical Reference Manual 5.13.4 IrDA Mode The UART supports IrDA SIR (Serial Infrared) Transmit Encoder and Receive Decoder. IrDA mode is selected by setting the UART_FUNCSEL.IRDAENbit. When in IrDA mode, the UART_BAUD.BAUDM1 register must be zero and baud rate is given by: Baud Rate = UART_CLK / (16 * BRD), where BRD is Baud Rate Divider in the UART_BAUD.BRD...
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ISD91200 Series Technical Reference Manual STOP BIT START BIT SOUT (from uart TX) Timing IR_SOUT (encoder output) 3/16 bit width IR_SIN (decorder input) Timing 3/16 bit width (To uart RX) START BIT STOP BIT Bit pulse width Figure 5-75 IrDA Tx/Rx Timing Diagram...
ISD91200 Series Technical Reference Manual 5.13.5 LIN (Local Interconnection Network) mode The UART supports a Local Interconnection Network (LIN) function. LIN mode is selected by setting the UART_FUNCSEL.LINEN bit. In LIN mode, each byte field is initiated by a start bit with value zero...
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ISD91200 Series Technical Reference Manual Buffer Error Interrupt Enable BUFERRIEN 0 = Mask off BUFERRINT. 1 = Enable IBUFERRINT. Receive Time Out Interrupt Enable RXTOIEN 0 = Mask off RXTOINT. 1 = Enable RXTOINT. Modem Status Interrupt Enable MODEMIEN 0 = Mask off MODEMINT.
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ISD91200 Series Technical Reference Manual FIFO Control Register (UARTn_FIFO) Register Offset Description Reset Value UARTn_FIFO UARTn_BA+0x08 R/W UART FIFO Control Register. 0x0000_0000 Reserved Reserved RTSTRGLV Reserved RFITL Reserved TXRST RXRST Reserved Table 5-119 UART FIFO Control Register (UARTn_FIFO, address 0x4005_0008)
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ISD91200 Series Technical Reference Manual Receive FIFO Reset When RXRST is set, all the bytes in the receive FIFO are cleared and receive internal state machine is reset. RXRST 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the receiving internal state machine and pointers.
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ISD91200 Series Technical Reference Manual Line Control Register (UARTn_LINE) Register Offset Description Reset Value UARTn_LINE UARTn_BA+0x0C R/W UART Line Control Register. 0x0000_0000 Reserved Table 5-120 UART Line Control Register (UARTn_LINE, address 0x4005_000C) Bits Description [31:7] Reserved Reserved. Break Control Bit When this bit is set to logic 1, the serial data output (Tx) is forced to the ‘Space’...
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ISD91200 Series Technical Reference Manual MODEM Control Register (UARTn_MODEM) Register Offset Description Reset Value UARTn_MODEM UARTn_BA+0x10 R/W UART Modem Control Register. 0x0000_0000 Reserved Reserved Reserved RTSSTS Reserved RTSACTLV Reserved Reserved LBMEN Reserved Reserved Table 5-121 UART Modem Control Register (UARTn_MODEM, address 0x4005_0010)
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ISD91200 Series Technical Reference Manual Modem Status Register (UARTn_MODEMSTS) Register Offset R/W Description Reset Value UARTn_MODEMSTS UARTn_BA+0x14 R/W UART Modem Status Register. 0x0000_0010 Reserved Reserved Reserved CTSACTLV Reserved CTSSTS Reserved CTSDETF Table 5-122 UART Modem Status Register (UARTn_MODEMSTS, address 0x4005_0014)
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ISD91200 Series Technical Reference Manual FIFO Status Register (UARTn_FIFOSTS) Register Offset Description Reset Value UARTn_FIFOSTS UARTn_BA+0x18 R/W UART FIFO Status Register. 0x1040_4000 Reserved TXEMPTYF Reserved TXOVIF TXFULL TXEMPTY TXPTR RXFULL RXEMPTY RXPTR Reserved Reserved RXOVIF Table 5-123 UART FIFO Status Register (UARTn_FIFOSTS, address 0x4005_0018)
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ISD91200 Series Technical Reference Manual Receive FIFO Full (Read Only) [15] RXFULL This bit indicates whether the Rx FIFO is full or not. This bit is set when Rx FIFO is full; otherwise it is cleared by hardware. Receive FIFO Empty (Read Only) This bit indicates whether the Rx FIFO is empty or not.
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ISD91200 Series Technical Reference Manual DMA MODE Buffer Error Interrupt Flag (Read Only) This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be [21] DBERRIF corrupted.
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ISD91200 Series Technical Reference Manual Buffer Error Interrupt Flag (Read Only) This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be BUFERRIF corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated.
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ISD91200 Series Technical Reference Manual When the DMA controller is used to transmit or receive data to the UART, an alternate set of flags and interrupt indicators are generated. These are equivalent to the normal mode set above and are summarized in below tables.
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ISD91200 Series Technical Reference Manual Time Out Register (UARTn_TOUT) Register Offset Description Reset Value UARTn_BA+0x20 R/W UART Time Out Register UARTn_TOUT 0x0000_0000 Reserved Reserved Reserved Reserved TOIC Table 5-127 UART Time Out Register (UARTn_TOUT, address 0x4005_0020) Bits Description [31:7] Reserved Reserved.
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ISD91200 Series Technical Reference Manual Baud Rate Divider Register (UARTn_BAUD) Register Offset Description Reset Value UARTn_BA+0x24 R/W UART Baud Rate Divisor Register UARTn_BAUD 0x0F00_0000 The baud rate generator takes the UART master clock UART_CLK and divides it to produce the baud rate (bit rate) clock.
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ISD91200 Series Technical Reference Manual IrDA Control Register (UARTn_IRDA) Register Offset Description Reset Value UARTn_IRDA UARTn_BA+0x28 R/W UART IrDA Control Register. 0x0000_0040 Reserved RXINV TXINV Reserved LOOPBACK TXEN Reserved Table 5-129 UART IrDA Control Register (UARTn_IRDA, address 0x4005_0028) Bits Description...
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ISD91200 Series Technical Reference Manual UART LIN Network Control Register (UARTn_ALTCTL) Register Offset Description Reset Value UARTn_ALTCTL UARTn_BA+0x2C R/W UART LIN Control Register. 0x0000_0000 Reserved Reserved Reserved LINTXEN LINRXEN Reserved BRKFL Table 5-130 UART LIN Network Control Register (UARTn_ALTCTL, address 0x4005_002C)
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ISD91200 Series Technical Reference Manual UART Function Select Register (UARTn_FUNCSEL) Register Offset Description Reset Value UARTn_FUNCSEL UARTn_BA+0x30 R/W UART Function Select Register. 0x0000_0000 Reserved Reserved Reserved Reserved IRDAEN LINEN Table 5-131 UART Function Select Register (UARTn_FUNCSEL, address 0x4005_0030) Bits Description...
ISD91200 Series Technical Reference Manual 5.14 I2S Audio PCM Controller 5.14.1 Overview The I2S controller is a peripheral for serial transmission and reception of audio PCM (Pulse-Code Modulated) signals across a 4-wire bus. The bus consists of a bit clock (I2S_BCLK) a frame synchronization clock (I2S_FS) and serial data in (I2S_SDI) and out (I2S_SDO) lines.
ISD91200 Series Technical Reference Manual 5.14.4 I2S Operation I2S_BCLK I2S_FS I2S_SDI I2S_SDO Word N-1 Word N Word N Right Channel Left Channel Right Channel Figure 5-79 I2S Bus Timing Diagram (Format =0) I2S_BCLK I2S_FS I2S_SDI I2S_SDO Word N-1 Word N...
ISD91200 Series Technical Reference Manual 5.14.5 FIFO operation Mono 16-bit data mode Stereo 16-bit data mode LEFT RIGHT Mono 24-bit data mode Stereo 24-bit data mode LEFT RIGHT Mono 32-bit data mode Stereo 32-bit data mode LEFT RIGHT Figure 5-81 FIFO contents for various I2S modes...
ISD91200 Series Technical Reference Manual 5.14.7 Register Description I2S Control Register (I2S_CTL) Register Offset Description Reset Value I2S_CTL I2S_BA + 0x00 I2S Control Register 0x0000_0000 Reserved Reserved Reserved RXPDMAEN TXPDMAEN RXCLR TXCLR LZCEN RZCEN MCLKEN RXTH TXTH SLAVE FORMAT MONO...
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ISD91200 Series Technical Reference Manual Right Channel Zero Cross Detect Enable If this bit is set to 1, when right channel data sign bit changes, or data bits are all zero, the RZCIF flag in I2S_STATUS register will be set to 1.
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ISD91200 Series Technical Reference Manual Receive Enable RXEN 0 = Disable data receive. 1 = Enable data receive. Transmit Enable TXEN 0 = Disable data transmit. 1 = Enable data transmit. Enable I2S Controller I2SEN 0 = Disable. 1 = Enable.
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ISD91200 Series Technical Reference Manual Receive FIFO Underflow Interrupt Enable If software read receive FIFO when it is empty then RXUDIF flag in I2SSTATUS register is set to 1. RXUDIEN 0 = Disable interrupt. 1 = Enable interrupt. Release Date: Sep 16, 2019 - 324 - Revision 2.4...
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ISD91200 Series Technical Reference Manual Transmit FIFO Threshold Flag (Read Only) When data word(s) in transmit FIFO is less than or equal to the threshold value set in TXTH[2:0] the TXTHIF bit becomes to 1. It remains set until transmit FIFO level is greater than TXTH[2:0].
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ISD91200 Series Technical Reference Manual I2S Transmit Interrupt (Read Only) This indicates that there is an active transmit interrupt source. This could be TXOVIF, TXUDIF, TXTHIF, LZCIF or RZCIF if corresponding interrupt enable bits TXIF are active. To clear interrupt the corresponding source(s) must be cleared.
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ISD91200 Series Technical Reference Manual I2S Transmit FIFO (I2S_TX) Register Offset Description Reset Value I2S_TX I2S_BA + 0x10 I2S Transmit FIFO Register 0xXXXX_XXXX Table 5-136 I2S Transmit FIFO Register (I2S_TX, address 0x400A_0010) Bits Description Transmit FIFO Register (Write Only) A write to this register pushes data onto the transmit FIFO. The transmit FIFO is [31:0] eight words deep.
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ISD91200 Series Technical Reference Manual I2S Receive FIFO (I2S_RX) Register Offset Description Reset Value I2S_RX I2S_BA + 0x14 I2S Receive FIFO Register 0xXXXX_XXXX Table 5-137 I2S Receive FIFO Register (I2S_RX, address 0x400A_0014) Bits Description Receive FIFO Register (Read Only) A read of this register will pop data from the receive FIFO. The receive FIFO is eight [31:0] words deep.
ISD91200 Series Technical Reference Manual 5.15 PDMA Controller 5.15.1 Overview The I91200 incorporates a Peripheral Direct Memory Access (PDMA) controller that transfers data between SRAM and APB devices. The PDMA has four channels of DMA PDMA CH0~CH3). PDMA transfers are unidirectional and can be Peripheral-to-SRAM,SRAM-to-Peripheral or SRAM-to-SRAM.
ISD91200 Series Technical Reference Manual 5.15.4 Function Description The PDMA controller has four channels of DMA, each channel can be configured to one of the following transfer types: Peripheral-to-SRAM SRAM-to-Peripheral or SRAM-to-SRAM. The SRAM and the AHB- APB bus bridge each have an AHB bus arbiter that allows AHB bus access to occur either from the CPU or the PDMA controller.
ISD91200 Series Technical Reference Manual 5.15.5 Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Offset R/W Description Reset Value PDMA Base Address: PDMAn_BA = 0x5000_8000 +(n*0x100) n=0,1,2,3...
ISD91200 Series Technical Reference Manual 5.15.6 Register Description PDMA Control Register (PDMA_CTLn) Register Offset Description Reset Value PDMA_CTLn PDMAn_BA+0x00 R/W PDMA Control Register of Channel n 0x0000_0000 Reserved TXEN Reserved TXWIDTH Reserved WAINTSEL Reserved DASEL SASEL MODESEL SWRST CHEN Table 5-138 PDMA Control and Status Register (...
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ISD91200 Series Technical Reference Manual Wrap Interrupt Select x1xx: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if PDMA_TXCNTn = 32 then an interrupt could be generated when 16 bytes were sent.
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ISD91200 Series Technical Reference Manual PDMA Channel Enable Setting this bit to 1 enables PDMA’s operation. If this bit is cleared, PDMA will ignore CHEN all PDMA request and force Bus Master into IDLE state. Note: SWRST will clear this bit.
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ISD91200 Series Technical Reference Manual PDMA Transfer Source Address Register (PDMA_SADDRn) Register Offset R/W Description Reset Value PDMA_SADDRn PDMAn_BA+0x04 R/W PDMA Transfer Source Address Register of Channel n 0x4000_0000 SADDR SADDR SADDR SADDR Table 5-139 PDMA Source Address Register (PDMA_DADDRn, address 0x5000_8004 + n*0x100)
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ISD91200 Series Technical Reference Manual PDMA Transfer Destination Address Register (PDMA_DADDRn) Register Offset R/W Description Reset Value PDMA_DADDRn PDMAn_BA+0x08 R/W PDMA Transfer Destination Address Register of Channel n 0x4000_0000 Table 5-140 PDMA Address Register (PDMAT_DADDRn, address 0x5000_8008 + n*0x100) Destination...
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ISD91200 Series Technical Reference Manual PDMA Transfer Byte Count Register (PDMA_TXCNTn) Register Offset Description Reset Value PDMA_TXCNTn PDMAn_BA+0x0C R/W PDMA Transfer Byte Count Register of Channel n 0x0000_0000 Reserved Reserved CNT [15:8] CNT [7:0] Table 5-141 PDMA (PDMA_TXCNTn, address 0x5000_800C + n*0x100)
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ISD91200 Series Technical Reference Manual PDMA Internal Buffer Pointer Register (PDMA_INTPNTn) Register Offset Description Reset Value PDMA_INTPNTn PDMAn_BA+0x10 R PDMA Internal Buffer Pointer Register of Channel n 0xXXXX_XX00 Reserved Reserved Reserved Reserved POINTER Table 5-142 PDMA Internal Buffer Point Register (PDMA_INTPNTn, address 0x5000_8010 + n*0x100)
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ISD91200 Series Technical Reference Manual PDMA Current Source Address Register (PDMA_CURSADDRn) ) Register Offset Description Reset Value PDMA_CURSADDRn PDMAn_BA+0x14 R PDMA Current Source Address Register of Channel n 0xFFFF_FFFF Table 5-143 PDMA Current Source Address Register (PDMA_CURSADDRn, address 0x5000_8014 +...
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ISD91200 Series Technical Reference Manual PDMA Current Destination Address Register (PDMA_CURDADDRn) Register Offset Description Reset Value PDMA_CURDADDRn PDMAn_BA+0x18 R PDMA Current Destination Address Register of Channel n 0xFFFF_FFFF Table 5-144 PDMA Current Destination Address Register (PDMA_CURDADDRn, address 0x5000_8018 + n*0x100)
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ISD91200 Series Technical Reference Manual PDMA Current Transfer Byte Count Register (PDMA_CURTXCNTn) Register Offset Description Reset Value PDMA_CURTXCNTn PDMAn_BA+0x1C R PDMA Current Transfer Byte Count Register of Channel n 0x0000_0000 Reserved Reserved Table 5-145 PDMA (PDMA_CURTXCNTn, address 0x5000_801C + Current Byte Count Register...
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ISD91200 Series Technical Reference Manual PDMA Interrupt Enable Control Register (PDMA_INTENn) Register Offset Description Reset Value PDMA_INTENn PDMAn_BA+0x20 R/W PDMA Interrupt Enable Control Register of Channel n 0x0000_0001 Reserved Reserved Reserved Reserved WRAPIEN TXIEN ABTIEN Table 5-146 PDMA (PDMA_INTENn, address 0x5000_8020 + n*0x100)
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ISD91200 Series Technical Reference Manual PDMA Interrupt Status Register (PDMA_INTSTSn) Register Offset Description Reset Value PDMA_INTSTSn PDMAn_BA+0x24 R/W PDMA Interrupt Status Register of Channel n 0x0000_0000 INTSTS Reserved Reserved Reserved WRAPIF Reserved TXIF ABTIF Table 5-147 PDMA Interrupt Enable Status Register (PDMA_INTSTSn, address 0x5000_8024 +...
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ISD91200 Series Technical Reference Manual PDMA Current Span Increment Register (PDMA_CURSPANn) Register Offset R/W Description Reset Value PDMA_CURSPANn PDMAn_BA+0x38 R/W PDMA Current Span Increment Register of Channel n 0x0000_0000 Reserved Reserved Reserved SPAN Table 5-149 PDMA Current Register (PDMA_CURSPANn, address 0x5000_8038 +...
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ISD91200 Series Technical Reference Manual PDMA Global Control Register (PDMA_GCTL) Register Offset Description Reset Value PDMA_GCTL PDMA_GCR_BA+0x00 PDMA Global Control Register 0x0000_0000 Reserved Reserved Reserved CH3CKEN CH2CKEN CH1CKEN CH0CKEN Reserved SWRST Table 5-150 PDMA (PDMA_GCTL, address 0x5000_8F00) Global Control Register...
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ISD91200 Series Technical Reference Manual PDMA Service Selection Control Register 0(PDMA_SVCSEL0) Register Offset Description Reset Value PDMA_SVCSEL0 PDMA_GCR_BA+0x04 PDMA Service Selection Control Register 0 0xFFFF_FFFF PDMA peripherals have transmit and/or receive request signals to control dataflow during PDMA transfers. These signals must be connected to the PDMA channel assigned by software for use with that peripheral.
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ISD91200 Series Technical Reference Manual PDMA SPI0 Receive Selection [3:0] SPI0RXSEL This field defines which PDMA channel is connected to SPI0 peripheral receive (PDMA source) request. Release Date: Sep 16, 2019 - 349 - Revision 2.4...
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ISD91200 Series Technical Reference Manual PDMA Service Selection Control Register 1(PDMA_SVCSEL1) Register Offset Description Reset Value PDMA_SVCSEL1 PDMA_GCR_BA+0x08 PDMA Service Selection Control Register 1 0xFFFF_FFFF PDMA peripherals have transmit and/or receive request signals to control dataflow during PDMA transfers. These signals must be connected to the PDMA channel assigned by software for use with that peripheral.
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ISD91200 Series Technical Reference Manual PDMA Global Interrupt Status Register (PDMA_GINTSTS) Register Offset Description Reset Value PDMA_GINTSTS PDMA_GCR_BA+0x0C PDMA Global Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved CH3INTSTS CH2INTSTS CH1INTSTS CH0INTSTS Table 5-153 PDMA (PDMA_GINTSTS, address 0x5000_8F0C) Global Interrupt Status Register...
ISD91200 Series Technical Reference Manual 5.16 Volume Control 5.16.1 Overview and feature The volume control function is digital domain gain control and supports both side of SDADC and DPWM. The audio signal can be changed from 36 dB to -108dB if using this feature.
ISD91200 Series Technical Reference Manual 5.16.3 Volume Control register Description Volume Control Enable Register (VOLCTRL_EN) Register Offset R/W Description Reset Value VOLCTRL_EN VOLCTRL_BA+0x00 R/W Volume Control Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved DPWMZCEN SDADCZCEN DPWMVOLEN SDADCVOLE Bits Description [31:4]...
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ISD91200 Series Technical Reference Manual ADC Volume Control Value(VOLCTRL_ADCVAL) Register Offset R/W Description Reset Value VOLCTRL_ADCVAL VOLCTRL_BA+0x04 R/W ADC Volume Control Value 0x0004_0000 Reserved VALUE VALUE VALUE Bits Description [31:24] Reserved Reserved Delta-Sigma ADC Signal Volume Control Value Format <6,18>, gain range from -108.3dB to 36.1dB 0x00_0001 --- -108.3dB...
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ISD91200 Series Technical Reference Manual DAC Volume Control Value (VOLCTRL_DPWMVAL) Register Offset R/W Description Reset Value VOLCTRL_DPWMVAL VOLCTRL_BA+0x08 R/W DPWM Volume Control Value 0x0004_0000 Reserved VALUE VALUE VALUE Bits Description [31:24] Reserved DPWM Audio Signal Volume Control Value Format <6,18>. Gain range from 108.3dB to 36.1dB 0x00_0001 ---- -108.3dB...
ISD91200 Series Technical Reference Manual FLASH MEMORY CONTROLLER (FMC) Overview The I91200 series is available with 64K/128K bytes of on-chip embedded Flash EEPROM for application program and data flash memory. The memory can be updated through procedures for In- Circuit Programming (ICP) through the ARM Serial-Wire Debug (SWD) port or via In-System Programming (ISP) functions under software control.
ISD91200 Series Technical Reference Manual Flash Memory Controller Block Diagram The flash memory controller consist of AHB slave interface, ISP control logic, writer interface and flash macro interface timing control logic. The block diagram of flash memory controller is shown as...
ISD91200 Series Technical Reference Manual Flash Memory Organization The I91200 flash memory consists of Application Program (APROM) memory (128/64KB), data flash (DATAF), ISP boot loader (LDROM) program memory (4KB), user configuration (CONFIG). User configuration block provides 2 words that control system configuration, like flash security lock, boot select, brown out voltage level and data flash base address.
ISD91200 Series Technical Reference Manual UART, SPI or I2C to fetch new application code. The memory area from which the I91200 boots is controlled by the CBS bit in Config0 register. Data Flash (DATAF) The I91200 provides a data flash partition for user to store non-volatile data such as audio recordings. It accessed through ISP procedures via the Flash Memory Controller (FMC).
ISD91200 Series Technical Reference Manual In-System Programming (ISP) The program and data flash memory support both in hardware In-Circuit Programming (ICP) and firmware based In-System programming (ISP). Hardware ICP programming mode uses the Serial-Wire Debug (SWD) port to program chip. Dedicated ICE Debug hardware or ICP gang-writers are available to reduce programming and manufacturing costs.
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ISD91200 Series Technical Reference Manual Power CBS = 1 ? Enable ISPEN Write ISPADR/ ISPCMD/ Fetch code from Fetch code from ISPDAT LDROM APROM Set ISPTRIG = 1 Update LD-ROM or Execute ISP? write DataFlash End of Flash Operation (Read ISPDAT)
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ISD91200 Series Technical Reference Manual Read Company ID 0x0B Returns 0x0000_00DA Read Device ID 0x0C 0x00000 FLASH Page Erase 0x22 A[20] A[19:0] FLASH Program 0x21 A[20] A[19:0] Data input FLASH Read 0x00 A[20] A[19:0] Data output CONFIG Page Erase 0x22...
ISD91200 Series Technical Reference Manual 6.10 Register Description ISP Control Register (FMC_ISPCTL) The FMC_ISPCTL register is a protected register, user must first follow the unlock sequence to gain access. Register Offset Description Reset Value FMC_ISPCTL FMC_BA+0x00 ISP Control Register 0x0002_0000...
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ISD91200 Series Technical Reference Manual Reserved Reserved. Boot Select 0 = APROM. 1 = LDROM. Modify this bit to select which ROM next boot is to occur. This bit also functions as MCU boot status flag, which can be used to check where MCU booted from. This bit is initialized after power-on reset with the inverse of CBS in Config0;...
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ISD91200 Series Technical Reference Manual ISP Address Register (FMC_ISPADDR) Register Offset Description Reset Value FMC_ISPADDR FMC_BA+0x04 ISP Address Register 0x0000_0000 ISPADDR ISPADDR ISPADDR ISPADDR Table 6-7 ISP Address Register (FMC_ISPADDR, address 0x5000_C004) Bits Description ISP Address Register This is the memory address register that a subsequent ISP command will access.
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ISD91200 Series Technical Reference Manual ISP Data Register (FMC_ISPDAT) Register Offset Description Reset Value FMC_ISPDAT FMC_BA+0x08 ISP Data Register 0x0000_0000 ISPDAT ISPDAT ISPDAT ISPDAT Table 6-8 ISP Data Register (FMC_ISPDAT, address 0x5000_C008) Bits Description ISP Data Register [31:0] ISPDAT Write data to this register before an ISP program operation.
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ISD91200 Series Technical Reference Manual ISP Trigger Control Register (FMC_ISPTRG) The FMC_ISPTRG register is a protected register, user must first follow the unlock sequence to gain access. Register Offset Description Reset Value FMC_ISPTRG FMC_BA+0x10 ISP Trigger Control Register 0x0000_0000 Reserved...
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ISD91200 Series Technical Reference Manual Data Flash Base Address Register (FMC_DFBA) Register Offset Description Reset Value FMC_DFBA FMC_BA+0x14 Data Flash Base Address 0xXXXX_XXXX DFBA DFBA DFBA DFBA Table 6-11 Data Flash Base Address Register (FMC_DFBA, address 0x5000_C014) Bits Description Data Flash Base Address This register reports the data flash starting address.
ISD91200 Series Technical Reference Manual ANALOG SIGNAL PATH BLOCKS This section describes the functional blocks that perform analog signal functions on the ISD91200. This includes the ADC, DPWM Speaker Driver, PGA Gain Amplifier, Automatic Gain Control and a variety of auxiliary analog functional blocks.
ISD91200 Series Technical Reference Manual 7.1.4 Operation The SDADC is an audio Sigma-Delta converter that operates by oversampling the analog input at low resolution and decimating the result by an over-sampling ratio to obtain a high resolution output which is pushed into the FIFO. The ultimate data rate is determined by the converter clock frequency, and the oversampling ratio.
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ISD91200 Series Technical Reference Manual • Setup FIFO data width SDADC_CTL.FIFOBITS • Setup down ampling rate, set SDADC_CTL.RATESEL=0 then set SDADC_CTL.DSRATE & BIQ_CTL.SDADCWNSR for expected DSR & sampling rate(refer to Table 7-1) • Setup PDMA channel to receive data from SDADC.
ISD91200 Series Technical Reference Manual 7.1.4.5 Peripheral DMA Request Normal use of the SDADC is with PDMA. In this mode ADC requests PDMA service whenever data is in FIFO. PDMA channel will copy this data to a buffer and alert the CPU when buffer is full. In this way an entire buffer of data can be collected without any CPU intervention.
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ISD91200 Series Technical Reference Manual SD ADC Clock Divider Register (SDADC_CLKDIV) Register Offset Description Reset Value SDADC_CLKDIV SDADC_BA+0x08 R/W SD ADC Clock Divider Register 0x0000_0000 Reserved Reserved Reserved CLKDIV[7:0] Bits Description [31:8] Reserved Reserved. SD_CLK Clock Divider SDADC internal clock divider. CLKDIV should be set to give a SD_CLK frequency in the range of 1.024-6.144MHz.
ISD91200 Series Technical Reference Manual Bridge Sense 7.2.1 Functional Description The Bridge Sense block consists of three parts, a low noise bandgap, an LDO and an Instrumentation Amplifier (IA). See Figure 3 for the block diagram. The bandgap circuit generates a reference voltage, VBG. The LDO uses VBG to make a stable voltage that can be used to bias a Wheatstone bridge.
ISD91200 Series Technical Reference Manual Figure 4. Block diagram of instrumentation amplifier (IA). 7.2.4 Operation 7.2.4.1 Startup To power on the bridge sense part of the I92160B the bridge sense bandgap and the LDO have to be turned on first.
ISD91200 Series Technical Reference Manual Following are compensation examples for Offset Minimum Calibration. Step1: Set bit INSTRAMP[10] =1 (BS Instrumentation Amplifier offset negative input opamp enable), (note INSTRAMP[11] =0 ) Step2: Set bit INSTRAMP[9:4] = 0x3f ,code 0x20 doesn’t exist Step3: Ignore the next 64 output cycles, for signal stable Step4: Capture 64 cycles of output data and average store them in an array ;...
ISD91200 Series Technical Reference Manual Register Offset Description Reset Value BS_BANDGPLDO SDADC_BA+0x24 R/W Bridge Sense Bandgap and LDO Control Register 0x0000_400e BS_INSTRAMP SDADC_BA+0x28 R/W Bridge Sense Instrumentation Amplifer Control Register 0x000c_0c00 7.2.6 Register Description Bridge Sense Bandgap and LDO Control Register(BS_BANDGP_LDO)
ISD91200 Series Technical Reference Manual Audio Class D Speaker Driver (DPWM) 7.3.1 Functional Description The ISD91200 includes a differential Class D (PWM) speaker driver capable of delivering 0.5W into an 8Ω load at 5V supply voltage. The driver works by up-sampling and modulating a PCM input to differentially drive the SPK+ and SPK- pins.
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ISD91200 Series Technical Reference Manual 7.3.4.1 DPWM switch frequecy HCLK DPWM_CLK= Switch frequency HCLK/DPWMDIV 49.152MHz 24.576MHz 614.4KHz 12.288MHz 307.2KHz 8.192MHz 204.8KHz 6.144MHz 153.6KHz 7.3.4.2 DPWM Clock Generator DPWMCKSEL(CLK_CLKSEL1[5:4]) DPWMCKEN(CLK_APBCLK0[13]) HCLK 1/(DPWMDIV + 1) DPWMDIV (CLK_CLKDIV0[15:12]) DPWM_CLK CLK12M Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
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ISD91200 Series Technical Reference Manual 16KHz 8KHz 7.3.4.4 Configuring Speaker Driver To operate the speaker driver the following configuration is recommended: • Enable DPWM clock source (CLK_APBCLK0.DPWMCKEN, CLK_CLKSEL1.DPWMCKSEL). • Reset DPWM IP block. (SYS_IPRST1.DPWMRST) • Select sample rate based on current DPWM_CLK frequency.
ISD91200 Series Technical Reference Manual Analog Functional Blocks 7.4.1 Overview The ISD91200 contains a variety of analog functional blocks that facilitate audio processing, enable analog GPIO functions (current source, relaxation oscillator, and comparator), adjust and measure internal oscillator and provide voltage regulation. These blocks are controlled by registers in the analog block address space.
ISD91200 Series Technical Reference Manual 7.4.4 VMID Reference Voltage Generation The analog path and blocks require a low when off. noise, mid-rail, Voltage reference for operation, the VMID generation block provides this. Control of this block allows user to power down the block, select its power down condition and control over the reference impedance.
ISD91200 Series Technical Reference Manual VMID Control Register (ANA_VMID) Register Offset Description Reset Value ANA_VMID ANA_BA+0x00 VMID Reference Control Register 0x0000_0007 Reserved PDHIRES PDLORES PULLDOWN Table 7-6 VMID Control Register (ANA_VMID, address 0x4008_0000). Bits Description [31:3] Reserved Reserved. Power Down High (360kΩ) Resistance Reference 0= Connect the High Resistance reference to VMID.
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ISD91200 Series Technical Reference Manual LDO Voltage Control Register (ANA_LDOSEL) Register Offset Description Reset Value ANA_LDOSEL ANA_BA+0x20 LDO Voltage Select Register 0x0000_0000 Reserved LDOSEL Table 7-7 , address 0x4008_0020). LDO Voltage Control Register ANA_LDOSEL Bits Description [31:3] Reserved Reserved. Select LDO Output Voltage Note that maximum I/O pad operation speed only specified for voltage >2.4V.
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ISD91200 Series Technical Reference Manual Oscillator Trim Register (ANA_TRIM) Register Offset Description Reset Value ANA_TRIM ANA_BA+0x84 Oscillator Trim Register 0x0000_XXXX Reserved Reserved COARSE OSCTRIM Table 7-11 Oscillator Trim Register (ANA_TRIM, address 0x4008_0084). Bits Description [31:16] Reserved Reserved. COARSE [15:8] COARSE Current COARSE range setting of the oscillator.
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ISD91200 Series Technical Reference Manual Frequency Measurement Control Register (ANA_FQMMCTL) Register Offset Description Reset Value ANA_FQMMCTL ANA_BA+0x94 Frequency Measurement Control Register 0x0000_0001 FQMMEN Reserved CYCLESEL Reserved Reserved MMSTS CLKSEL Table 7-12 Frequency Measurement Control Register (ANA_FQMMCTL, address 0x4008_0094). Bits Description...
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ISD91200 Series Technical Reference Manual Frequency Measurement Count (ANA_FQMMCNT) Register Offset Description Reset Value ANA_FQMMCNT ANA_BA+0x98 Frequency Measurement Count Register 0x0000_0000 Reserved Reserved FQMMCNT FQMMCNT Table 7-13 Frequency Measurement Count Register (ANA_FQMMCNT, address 0x4008_0098). Bits Description [31:16] Reserved Reserved. Frequency Measurement Count When MMSTS = 1 and FQMMEN = 1, this is number of PCLK periods counted for frequency measurement.
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ISD91200 Series Technical Reference Manual Frequency Measurement Cycle (ANA_FQMMCYC) Register Offset Description Reset Value ANA_FQMMCYC ANA_BA+0x9C Frequency Measurement Cycle Register 0x0000_0000 Reserved FQMMCYC FQMMCYC FQMMCYC Table 7-14 Frequency Measurement Cycle Register (ANA_FQMMCYC, address 0x4008_009C). Bits Description [31:24] Reserved Reserved. Frequency Measurement Cycles Number of reference clock periods plus one to measure target clock (PCLK).
ISD91200 Series Technical Reference Manual Automatic Level Control (ALC) 7.5.1 Overview and Features The SDADC audio signal digital path is supported by digital automatic level control function. The ALC monitors the output of the SDADC biquad output when that filter is enabled in the SDADC path, or the output of the SINC filter otherwise.
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ISD91200 Series Technical Reference Manual In Normal mode, the MAXGAIN bits set the maximum level for the PGA but in the Limiter mode MAXGAIN has no effect because the maximum level is set by the initial PGA gain setting upon enabling of the ALC.
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ISD91200 Series Technical Reference Manual In limiter mode, the PGA gain is constrained to be less than or equal to the gain setting at the time the limiter mode is enabled. In addition, attack and decay times are faster in limiter mode than in normal mode as indicated by the different lookup tables for these parameters for limiter mode.
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ISD91200 Series Technical Reference Manual PGA Input PGA Output PGA Gain Figure 7-14: ALC Operation with Noise Gate disabled PGA Input Noise Gate Threshold PGA Output PGA Gain Figure 7-15: ALC Operation with Noise Gate Enabled 7.5.1.7 Zero Crossing The PGA gain comes from either the ALC block when it is enabled or from the PGA gain register setting when the ALC is disabled.
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ISD91200 Series Technical Reference Manual ALC Initial Gain Set ALC initial gain. [5:0] INITGAIN Selects the PGA gain setting from -12dB to 35.25dB in 0.75dB step size. 0x00 is lowest gain setting at -12dB and 0x3F is largest gain at 35.25dB...
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ISD91200 Series Technical Reference Manual ALC Status Register (ALC_STATUS) Register Offset Description Reset Value ALC_STS ALC_BA+0x08 ALC Status Register 0x0100_0000 Table 7-17 ALC Status Register (ALC_STS, address 0x400B_0098) Reserved ALCGAIN ALCGAIN PEAKVAL[8:5] PEAKVAL[4:0] P2PVAL[8:6] P2PVAL[5:0] NOISEF CLIPF Bits Description [31:26] Reserved Reserved.
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ISD91200 Series Technical Reference Manual Reserved GMINIE GMAXIE GDECIE GINCIE NGIE PLMTIE Bits Description ALC Interrupt flag This interrupt flag asserts whenever the interrupt is enabled and the PGA gain is [31] ALCIF updated, either through an ALC change with the ALC enabled or through a PGA gain write with the ALC disabled.
ISD91200 Series Technical Reference Manual Capacitive Sensing Scan (CSCAN) and Operational Amplifiers 7.6.1 Overview and Features Capacitive Sensing Scanner has the ability to set up a capacitive sensing on up to 16 GPIO pins. The block can do a single measurement or be set up to scan a defined set of GPIO before interrupting the CPU.
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ISD91200 Series Technical Reference Manual A0PSEL 00: no connection 01: from VH1 (0.9×V 10: from VM (0.5×V 11: from VL1 (0.1×V no connection A0O2A1N A0O2N A0NS A0O2A1P OPA1 Connect To OPA0 SAR ADC8 A0PS A0OEN Figure 7-16 Operational Amplifier 0 Switch Control The following diagram and table illustrate the OPA1 switch control setting and the corresponding connections.
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ISD91200 Series Technical Reference Manual A1PSEL 00: no connection 01: from VH1 (0.9×V 10: from VM (0.5×V 11: from VL1 (0.1×V no connection A1O2N PGAEN 560k A1NS Connect To OPA1 SAR ADC9 A1PS A1OEN A0O2A1N OPA0 A0O2A1P Figure 7-17 Operational Amplifier 1 Switch Control The following diagram is OPAs bias setting, If the OPBIASEN is set to “1”, that will turn on the resistor DC path,...
ISD91200 Series Technical Reference Manual 7.6.5 Comparator The ISD91200 contains two analog comparators are contained within the devices. These functions offer flexibility via their register controlled features such as power-down, interrupt etc. Sharing their pins with normal I/O pins, the comparators do not waste precious I/O pins if there functions are otherwise unused.
ISD91200 Series Technical Reference Manual 7.6.7 Register Description CSCAN Control Register (CSCAN_CTRL) Register Offset Description Reset Value CSCAN_CTRL CSCAN_BA+0x00 R/W CSCAN Control Register 0x8000_0000 Table 7-19 CSCAN Control Register (CSCAN_CTRL, address 0x400D_0000) Reserved Reserved DUR_CNT MODE1 MODE0 SLOW_CLK INT_EN Reserved...
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ISD91200 Series Technical Reference Manual CSCAN Enable Interrupt [20] INT_EN 0 = Interrupt disabled. 1 = Interrupt enabled. [19:18] Reserved Keep with 0 CSCAN Oscillator current [17:16] CURRENT Controls the analog bais current of the capacitive relaxation oscillator. 0:300nA 1:450nA 2:600nA 3:1200nA...
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ISD91200 Series Technical Reference Manual CSCAN Cycle Count Number of cycles to time a CapSense even over 4 bit value decoded to 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 768, 1024, 1536, 2048, 2560, 3072 CYCLE_CNT Cycles...
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ISD91200 Series Technical Reference Manual Table 7-22 CSCAN Interrupt Register (CSCAN_INT, address 0x400D_000C) Reseverd Reserved Reserved Reserved Bits Description [31:1] Reserved CSCAN Interrupt active Write ‘1’ to clear. CSCAN Analog GPIO Register (CSCAN_AGPIO) Register Offset Description Reset Value CSCAN_AGPIO CSCAN_BA+0x10 R/W...
ISD91200 Series Technical Reference Manual Biquad Filter (BIQ) 7.7.1 Overview and Features A coefficient programmable 6-stage Biquad filter (12 -Order IIR filter) is available which can be used on either SDADC path or DPWM path to further reduce unwanted noise or filter the signal. Each biquad filter has the transfer function as H(z) and is implemented in Direct Form II Transpose structure as.
ISD91200 Series Technical Reference Manual Configuring Coefficient 1. BIQ function work on 6 stages, set BIQ_CTL.STAGE=0, BIQ function will call 30 coefficients from BIQ_BA+0x0 ~0x074 2. BIQ function work on 5 stages, set BIQ_CTL.STAGE=1, BIQ function will call 25 coefficients from BIQ_BA+0x00 ~0x060 3.
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ISD91200 Series Technical Reference Manual Coefficient b0 In H(z) Transfer Function BIQ_COEFF10 BIQ_BA + 0x28 0x0000_0000 (3.16 format) - 3 stage BIQ Coefficients Coefficient b1 In H(z) Transfer Function BIQ_COEFF11 BIQ_BA+0x02c 0x0000_0000 (3.16 format) - 3 stage BIQ Coefficients Coefficient b2 In H(z) Transfer Function...
ISD91200 Series Technical Reference Manual 7.7.3 Register Description BIQ Coefficient Register (BIQ_COEFFn) Register Offset Description Reset Value Coefficient b0 In H(z) Transfer Function BIQ_COEFF0 BIQ_BA+0x00 0x0000_0000 (3.16 format) - 1 stage BIQ Coefficients Coefficient b1 In H(z) Transfer Function BIQ_COEFF1...
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ISD91200 Series Technical Reference Manual Coefficient a2 In H(z) Transfer Function BIQ_COEFF19 BIQ_BA+0x04c 0x0000_0000 (3.16 format) - 4 stage BIQ Coefficients Coefficient b0 In H(z) Transfer Function BIQ_COEFF20 BIQ_BA + 0x50 0x0000_0000 (3.16 format) - 5 stage BIQ Coefficients Coefficient b1 In H(z) Transfer Function...
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ISD91200 Series Technical Reference Manual BIQ Control Register (BIQ_CTL) Register Offset Description Reset Value BIQ_CTL BIQ_BA+0x080 BIQ Control Register 0x0000_0110 Table 7-24 BIQ Control Register (BIQ_CTL, address 0x400B_0080) Reserved SRDIV[12:8] SRDIV[7:0] Reserved STAGE DPWMPUSR PRGCOEFF SDADCWNSR DLCOEFF PATHSEL HPFON BIQEN...
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ISD91200 Series Technical Reference Manual Move BIQ Out of Reset State 0 = BIQ filter is in reset state. DLCOEFF 1 = When this bit is on, the default coefficients will be downloaded to the coefficient ram automatically in 32 internal system clocks. Processor must delay enough time before changing the coefficients or turn the BIQ on.
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ISD91200 Series Technical Reference Manual BIQ Status Register (BIQ_STATUS) Register Offset Description Reset Value BIQ_STS BIQ_BA+0x084 BIQ status Register 0x8000_0000 Table 7-25 BIQ Status Register (BIQ_STATUS) RAMINITF Reserved Reserved Reserved Reserved BISTDONE BISTFAILED BISTEN Bits Description Coefficient Ram Initial Default Done Flag...
ISD91200 Series Technical Reference Manual Successive Approximation Analog-to-Digital Convertor (SARADC) 7.8.1 Overview and Features – Analog input voltage range: 0~VREF – Up to 12 single-end analog input channels – Three operating modes • Single mode: A/D conversion is performed one time on a specified channel.
ISD91200 Series Technical Reference Manual 7.8.2 Block Diagram VALID & OVERRUN PDMA request Digital Control Logics ADC_INT STADC & ADC Clock Generator RSLT[11:0] Successive Approximations Register 12-bit DAC ADC0 ADC1 Analog Control Logics Comparator ADC11 Sample and Hold Analog Macro Figure 7-20 SARADC Block Diagram 7.8.3...
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ISD91200 Series Technical Reference Manual 7.8.3.1 SARADC Clock Generator The SARADC engine has four clock sources selected by 2 bits SARADCSEL, the SARADC clock divided by 8 bits prescaler with the formula. The SARADC clock frequency = (SARADC clock source frequency)/(SARADCDIV+1).
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ISD91200 Series Technical Reference Manual ADC_CLK SWTRG sample ADDRx[11:0] ADDRx[11:0] ADEF Figure 7-22 Single Mode Conversion Timing Diagram 7.8.3.3 Single-Cycle Scan Mode In single-cycle scan mode, A/D conversion will sample and convert the specified channels once in the sequence from the smallest number enabled channel to the largest number enabled channel.
ISD91200 Series Technical Reference Manual 7.8.5 Register description SAR ADC Data Register (SARADC_DATx) Register Offset Description Reset Value SARADC_DAT0 SARADC_BA+0x00 SAR ADC Data Register 0 0x0000_0000 SARADC_DAT1 SARADC_BA+0x04 SAR ADC Data Register 1 0x0000_0000 SARADC_DAT2 SARADC_BA+0x08 SAR ADC Data Register 2...
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ISD91200 Series Technical Reference Manual Overrun Flag (Read Only) 0 = Data in RESULT[11:0] is recent conversion result. 1 = Data in RESULT[11:0] is overwritten. [16] Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1 and previous conversion result is gone.
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ISD91200 Series Technical Reference Manual SAR ADC Status Register ( SARADC_STATUS Register Offset R/W Description Reset Value SARADC_ST SARADC_BA+0x40 R/W SAR ADC status Register 0x0000_0000 ATUS Reserved VALID[15:8] VALID[7:0] CHANNEL BUSY ADCMPF1 ADCMPF0 ADEF Bits Description [31:24] Reserved Reserved. Data Valid Flag (Read Only)
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ISD91200 Series Technical Reference Manual SAR ADC PDMA Current Transfer Data Register (SARADC_PDMADAT) Register Offset R/W Description Reset Value SARADC_PD SARADC_BA+0x50 SAR ADC PDMA Current Transfer Data 0x0000_0000 MADAT Reserved Reserved DATA[17:16] DATA[15:8] DATA[7:0] Bits Description [31:18] Reserved Reserved. SAR ADC PDMA Current Transfer Data Register (Read Only) When PDMA transferring, read this register can monitor current PDMA transfer data.
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ISD91200 Series Technical Reference Manual SAR ADC Analog Control Register(SARADC_ACTL) Register Offset R/W Description Reset Value SARADC_A SARADC_BA+0x5C R/W SAR ADC analog control register 0x0000_0000 Reserved Reserved Reserved SAR_VREF Reserved Reserved Reserved Reserved SAR_SE_MODE Bits Description [31:18] Reserved reserved VREF selection...
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ISD91200 Series Technical Reference Manual SAR ADC Control Register(SARADC_CTL) Register Offset Description Reset Value SARADC_CTL SARADC_BA+0x60 R/W SAR ADC Control Register 0x0000_0000 Reserved Reserved Reserved Reserved SWTRG Reserved PDMAEN HWTRGEN HWTRGCOND HWTRGSEL OPMODE ADCIE ADCEN Bits Description [31] Reserved Reserved...
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ISD91200 Series Technical Reference Manual External Trigger Condition These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.
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ISD91200 Series Technical Reference Manual SAR ADC Compare Register 0/1 (SARADC_CMP0/SARADC_CMP1) Register Offset R/W Description Reset Value SARADC_CM SARADC_BA+0x68 R/W SAR ADC Compare Register 0 0x0000_0000 SARADC_CM SARADC_BA+0x6C R/W SAR ADC Compare Register 1 0x0000_0000 Reserved CMPDAT CMPDAT Reserved CMPMCNT...
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ISD91200 Series Technical Reference Manual Compare Channel Selection 0000 = Channel 0 conversion result is selected to be compared. 0001 = Channel 1 conversion result is selected to be compared. 0010 = Channel 2 conversion result is selected to be compared.
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ISD91200 Series Technical Reference Manual ORDERING INFORMATION 1 x x x x x x Temperature ISD Audio Product Family I: -40°C ~ +85°C Product Series 1: Cortex-M0 Package R: LQFP-64 Family ID Y: QFN-32 2: Family Series ID Feature Blank: Standard...
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ISD91200 Series Technical Reference Manual 11 REVISION HISTORY PAGE/ VERSION DATE DESCRIPTION CHAP. V0.2 Sep 1, 2017 Preliminary Release. Add CSCAN feature and operation, fix Table & Figure reference V0.21 Sep 5, 2017 errors V0.22 Sep 7, 2017 Add SAR_VREF bit and description - Rename flash sector size as page size V0.23...
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