Figure 6.7-5 Pwm Counter Clock Source Control; Figure 6.7-6 Pwm Independent Mode Architecture Diagram - Nuvoton ISD94124BYI Technical Reference Manual

Figure 6.7-6 and Figure 6.7-7 illustrate the architecture of PWM independent mode and
complementary mode. Both independent mode and complementary mode support PWMx_CH0
and PWMx_CH1 output channels in each PWM generator.
When PWM counter counts to value 0, or PERIOD (TIMERx_PWMPERIOD[15:0]), or CMP
(TIMERx_PWMCMPDAT[15:0]), an event will be generated and trigger the operations following,
such as PWM pulse (Pulse Generator), interrupt signal (Interrupt Generator) and triggering signal
for ADC to start conversion.
Output Control block manages PWM pulse output as well as interrupt events. Dead-Time Control
is available only in PWM complementary mode.
TMRx_PWMCLK

Figure 6.7-6 PWM Independent Mode Architecture Diagram

Sep 9, 2019
ISD94100 Series Technical Reference Manual
CLKSRC (TIMERx_PWMCLKSRC[2:0])
TMRx_CLK
000
TMR0_INT
001
TMR1_INT 010
TMR2_INT
011
TMR3_INT 100

Figure 6.7-5 PWM Counter Clock Source Control

Interrupt events
Trigger events
Comparator
Prescale Counter
Note:
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TMRx_PWMCLK
Interrupt
i
NVIC
Generator
Trigger
t
ADC
Generator
i
a
Pulse Output
i
Generator Control
denotes interrupt events
i
denotes trigger events
t
denotes interrupt, trigger and pulse generate events
a
TMx
(PWMx_CH0)
TMx_EXT
(PWMx_CH1)
Rev1.09