Register Description - Nuvoton ISD94124BYI Technical Reference Manual

6.7.8

Register Description

Timer Control Register (TIMERx_CTL)
Offset
Register
TIMER0_CTL TMR01_BA+0x00
TIMER1_CTL TMR01_BA+0x100
TIMER2_CTL TMR23_BA+0x00
TIMER3_CTL TMR23_BA+0x100
31 30
ICEDEBUG CNTEN
23 22
WKEN Reserved
15 14
7 6
Description
Bits
[31]
ICEDEBUG
[30]
CNTEN
INTEN
[29]
[28:27] OPMODE
Sep 9, 2019
ISD94100 Series Technical Reference Manual
R/W Description
R/W Timer0 Control Register
R/W Timer1 Control Register
R/W Timer2 Control Register
R/W Timer3 Control Register
29 28
INTEN OPMODE
21 20
TGLPINSEL PERIOSEL
13 12
Reserved
5 4
PSC
ICE Debug Mode Acknowledge Disable Control (Write Protected)
0 = ICE debug mode acknowledgement effects TIMER counting.
TIMER counter will be held while CPU is held by ICE.
1 = ICE debug mode acknowledgement Disabled.
TIMER counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Timer Counting Enable Bit
0 = Stops/Suspends counting.
1 = Starts counting.
Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep
counting from the last stop counting value.
Note2: This bit is auto-cleared
(TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0])
is generated.
Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can
read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
Timer Interrupt Enable Bit
0 = Timer time-out interrupt Disabled.
1 = Timer time-out interrupt Enabled.
Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer
interrupt signal is generated and inform to CPU.
Timer Counting Mode Select
Page 368 of 928
27 26
ACTSTS
Reserved
19 18
INTRGEN Reserved
11 10
3 2
by hardware in one-shot
Reset Value
0x0000_0005
0x0000_0005
0x0000_0005
0x0000_0005
25 24
EXTCNTEN
17 16
9 8
1 0
mode OPMODE
Rev1.09