Figure 6.16-11 Eadc0_St De-Bounce Timing Diagram - Nuvoton ISD94124BYI Technical Reference Manual

PCLK
EADC0_ST
EADC0_ST falling
detect
EADC0_ST rising
detect

Figure 6.16-11 EADC0_ST De-bounce Timing Diagram

6.16.5.10 ADC Extend Sampling Time
When ADC operation at high ADC clock rate, the sampling time of analog input voltage may not
enough if the analog channel has heavy loading to cause fully charge time is longer. User can set
extend sampling time by writing EXTSMPT (EADC_SCTLn[31:24], n=0~12) for each sample
module. The ADC extend sampling time is present between ADC controller judge which channel to
be converting and ADC start to conversion. The range of extend sampling time is from 0 ~255 ADC
clock. The extended sampling time is shown in Figure 6.16-12.
A/D clock
A/D converter
start
A/D converter
channel select
A/D converter
Sample/Hold
A/D converter
finish
ADIFn (INTPOS=0)
ADIFn (INTPOS=1)
Note: N = EXTSMPT (EADC_SCTLn[31:24], n=0~12) (Extend sampling cycle for each sample module)
ADIFn (EADC_STATUS2[3:0], n=0~3)
INTPOS (EADC_SCTLn[22], n=0~12)
Sep 9, 2019
ISD94100 Series Technical Reference Manual
2 PCLK 3 PCLK
Extend Sampling Time
(N ADC clocks)
1
Hold Sampling
Page 766 of 928
2 PCLK 3 PCLK
A/D Conversion
2
Hold
14 ADC clocks
3
Sampling
Rev1.09