Register Description - Nuvoton ISD94124BYI Technical Reference Manual

6.14.9 Register Description

SPI Control Register
(SPI0_CTL)
Register Offset
SPI0_CTL SPI0_BA+0x00
31 30
23 22
Reserved QUADIOEN
15 14
RXONLY HALFDPX
7 6
SUSPITV
Description
Bits
[31:23]
Reserved
[22]
QUADIOEN
[21] DUALIOEN
DATDIR
[20]
REORDER
[19]
[18] SLAVE
[17] UNITIEN
Sep 9, 2019
ISD94100 Series Technical Reference Manual
R/W Description
R/W SPI0 Control Register
29 28
Reserved
21 20
DUALIOEN DATDIR REORDER
13 12
LSB
5 4
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
Quad I/O Mode Enable Bit (Only Supported in SPI0)
0 = Quad I/O mode Disabled.
1 = Quad I/O mode Enabled.
Dual I/O Mode Enable Bit (Only Supported in SPI0)
0 = Dual I/O mode Disabled.
1 = Dual I/O mode Enabled.
Data Port Direction Control
This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad
transfer
0 = SPI data is input direction.
1 = SPI data is output direction.
Byte Reorder Function Enable Bit
0 = Byte Reorder function Disabled.
1 = Byte Reorder function Enabled. A byte suspend interval will be inserted among each
byte. The period of the byte suspend interval depends on the setting of SUSPITV.
Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
Slave Mode Control
0 = Master mode.
1 = Slave mode.
Unit Transfer Interrupt Enable Bit
0 = SPI unit transfer interrupt Disabled.
Page 710 of 928
27 26
19 18
SLAVE UNITIEN
11 10
DWIDTH
3 2
CLKPOL TXNEG RXNEG
Reset Value
0x0000_0034
25 24
17 16
TWOBIT
9 8
1 0
SPIEN
Rev1.09