Figure 6.16-3 Sample Module 4~12 Block Diagram - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc

Table of Contents

EADC0_ST pin signal

Disable hardware Trigger

ADINT0 interrupt EOC pulse

ADINT1 interrupt EOC pulse

Timer0 overflow pulse

Timer1 overflow pulse

Timer2 overflow pulse

Timer3 overflow pulse

TRGSEL(EADC_SCTL4[20:16])

TRGDLYDIV (EADC_SCTL4[7:6])

Figure 6.16-3 Sample Module 4~12 Block Diagram

The ADC conversion trigger sources in sample module 0~12 are listed below:

Write 1 to SWTRGn (EADC_SWTRG[n], n = 0~12)

External pin EADC0_ST

Timer0~3 overflow pulse triggers

ADINT0, ADINT1 ADC interrupt EOC (End of conversion) pulse triggers

PWM triggers

The ADINT0 or ADINT1 interrupt pulses are generated whenever the specific sample module ADC

EOC (End of conversion) pulse is generated. ADINT0 or ADINT1 interrupt pulse triggers can be fed

back to trigger another ADC conversion, and is useful if a continuous scan conversion is needed.

6.16.5.1 ADC Clock Generator

The maximum EADC clock frequency is up to 60 MHz and the maximum sampling rate is up to 2

The clock control of EADC is shown as Figure 6.16-4. The EADC peripheral clock source is from

HCLK clock, the ADC clock frequency is divided by an 8-bit pre-scalar with the following formula :

EADC clock frequency = (PCLK1) / (EADCDIV (CKL_CLKDIV0[23:16])+1)

ISD94100 Series Technical Reference Manual

EXTREN (EADC_SCTL4[4])

EXTFEN (EADC_SCTL4[5])

/1, /2, /4, /16

(EADC_SCTL4[15:8])

Page 759 of 928

Sample Module

(EADC_SCTL4[3:0]

SWTRG4~12 Software

Sample Module

Show Quick Links

Table of Contents