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EADC0_ST pin signal
Disable hardware Trigger
ADINT0 interrupt EOC pulse
ADINT1 interrupt EOC pulse
Timer0 overflow pulse
Timer1 overflow pulse
Timer2 overflow pulse
Timer3 overflow pulse
PWM0TG0
PWM0TG1
PWM0TG2
PWM0TG3
PWM0TG4
PWM0TG5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TRGSEL(EADC_SCTL0[20:16])
ADC_CLK
Sep 9, 2019
ISD94100 Series Technical Reference Manual
EXTREN (EADC_SCTL0[4])
EXTFEN (EADC_SCTL0[5])
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
reset pulse
10h
11h
12h
13h
14h
15h
8-bit Up
Counter
/1, /2, /4, /16
TRGDLYCNT
(EADC_SCTL0[15:8])
TRGDLYDIV (EADC_SCTL0[7:6])
Figure 6.16-2 Sample Module 0~3 Block Diagram
Page 758 of 928
Sample Module
reset
EOC0
CHSEL
(EADC_SCTL0[3:0])
ADC
SWTRG0~3 Software
Sample and
trigger
Priority
control
Logic
=
3
Sample Module
0
Sample
Module 0
Result
Register
DAT0
Double
Data
Register
DDAT0
EOC0
Rev1.09
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