Block Diagram; Basic Configuration; Figure 6.16-1 Adc Converter Block Diagram - Nuvoton ISD94124BYI Technical Reference Manual

6.16.3 Block Diagram

AV
DD
EADC0_CH0
EADC0_CH12

6.16.4 Basic Configuration


Clock source configuration
–
Select the clock divider number in EADCDIV (CLK_CLKDIV0[23:16]).
–
Enable EADC peripheral clock in EADCCKEN (CLK_APBCLK0[28]).

Reset configuration
–
Reset EADC controller in ADCRST (EADC_CTL[1]).

Pin configuration
Group Pin Name
EADC0_CH0
EADC0
EADC0_CH1
Sep 9, 2019
ISD94100 Series Technical Reference Manual
12-bit DAC
V
REF
Sample and Hold
CHSEL (EADC_SCTLn[4:0])
Digatal Control Logics
&
ADC Clock Generator
User write, EADC0_ST input,
ADC interrupt, Timer0~3,
PWM triggers

Figure 6.16-1 ADC Converter Block Diagram

GPIO
PA.0
PA.1
Page 756 of 928
+
Analog Control Logics
-
Comparator
Successive
Approximations Register
A/D result [11:0]
A/D Sample Module 12
A/D Sample Module 0
Result Register
VALID & OVERRUN
(EADC_DAT0)
Control Register
Trigger
(EADC_SCTL0)
Analog Macro
MFP
MFP2
MFP2
Rev1.09