Basic Configuration; Functional Description; Figure 6.10-2 Wwdt Clock Control - Nuvoton ISD94124BYI Technical Reference Manual

6.10.4 Basic Configuration


Clock source configuration
–
Select the source of WWDT peripheral clock in WWDTSEL (CLK_CLKSEL1[31:30])
–
Enable WWDT peripheral clock in WDTCKEN (CLK_APBCLK0[0]).
The WWDT clock control are shown in Figure 6.10-2.

6.10.5 Functional Description

The WWDT includes a 6-bit down counter with programmable prescale value to define different
WWDT time-out intervals. The clock source of 6-bit WWDT is based on system clock divide 2048
(HCLK/2048) or 10 kHz internal low speed RC oscillator (LIRC) with a programmable 11-bit
prescale counter value which controlled by PSCSEL (WWDT_CTL[11:8]). Also, the correlate of
PSCSEL (WWDT_CTL[11:8]) and prescale value are listed in the Table 6.10.5-1.
Prescaler Value
PSCSEL
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Sep 9, 2019
ISD94100 Series Technical Reference Manual
WWDTSEL (CLK_CLKSEL1[31:30])
WDTCKEN (CLK_APBCLK0[0])
10 kHz (LIRC)
11
HCLK/2048
10

Figure 6.10-2 WWDT Clock Control

Max. Time-Out Period
1
2
4
8
16
32
64
128 128 * 64 * T
192 192 * 64 * T
256 256 * 64 * T
384 384 * 64 * T
512 512 * 64 * T
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WWDT_CLK
Max. Time-Out Interval
1 * 64 * T
WWDT
2 * 64 * T
WWDT
4 * 64 * T
WWDT
8 * 64 * T
WWDT
16 * 64 * T
WWDT
32 * 64 * T
WWDT
64 * 64 * T
WWDT
WWDT
WWDT
WWDT
WWDT
WWDT
(WWDT_CLK=10 KHz)
6.4 ms
12.8 ms
25.6 ms
51.2 ms
102.4 ms
204.8 ms
409.6 ms
819.2 ms
1.2288 s
1.6384 s
2.4576 s
3.2768 s
Rev1.09