Digital Microphone Inputs (Dmic); Overview; Features; Block Diagram - Nuvoton ISD94124BYI Technical Reference Manual

6.19 Digital Microphone Inputs (DMIC)

6.19.1 Overview

Using the dual channel digital PDM (Pulse Density Modulation) microphone interface (DMIC_CLK0,
DMIC_DAT0, DMIC_CLK1 and DMIC_DAT1 pins) that are handled four digital PDM microphone
inputs. Both DMIC_DAT0 and DMIC_DAT1 inputs are able to handle two digital microphones by
selecting them alternately for each half of the clock cycle.

6.19.2 Features

The digital microphone interface use two wires (DMIC_DATn and DMIC_CLKn) to receive
information from digital microphones. The main features of DMIC includes:

Provides one 32-level FIFO data buffers for receiving.

Generates interrupt requests when buffer levels cross a programmable boundary.

Supports PDMA transfer.

Supports up to four channel digital microphones.

Both digital PDM microphone inputs can be used simultaneously.

6.19.3 Block Diagram

Control Register
Bus Clock Control

6.19.4 Basic Configuration


Clock source configuration
–
The source of DMIC peripheral clock is selected by DMICSEL (CLK_CLKSEL2[11:10]).
–
The DMIC peripheral clock is enabled by DMICCKEN (CLK_APBCLK0[15]).

Reset configuration
Sep 9, 2019
ISD94100 Series Technical Reference Manual
APB Interface
PDMA
Interface Control

Figure 6.19-1 DMIC Block Diagram

Page 866 of 928
DMIC_DATn
Buffer
DMIC_CLKn
Note: n = 0 or 1
Rev1.09