Figure 6.12-14 Uart Nrts Auto-Flow With Software Control - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc
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is directly controlled by software programming of RTS(UART_MODEM[1]) control bit.
Setting RTSACTLV (UART_MODEM[9]) can control the UART0_nRTS pin output is inverse or non-
inverse from RTS (UART_MODEM[1]) control bit. User can read the RTSSTS (UART_MODEM[13])
bit to get real nRTS pin output voltage logic status.
UART0_nRTS pin output status of UART function mode
Set UART_MODEM[1]=0
RTS control bit
(UART_MODEM[1])
RTSSTS
(UART_MODEM[13])
UART0_nRTS pin output

Figure 6.12-14 UART nRTS Auto-Flow with Software Control

6.12.5.9 RS-485 Function Mode
Another alternate function of UART controller is RS-485 function (user must set UART_FUNCSEL
[1:0] to '11' to enable RS-485 function), and direction control provided by nRTS pin from an
asynchronous serial port. The RS-485 transceiver control is implemented by using the nRTS control
signal to enable the RS-485 driver. Many characteristics of the RX and TX are same as UART in
RS-485 mode.
The UART controller can be configured as an RS-485 addressable slave and the RS-485 master
transmitter will identify an address character by setting the parity (9-th bit) to 1. For data characters,
the parity is set to 0. Software can use UART_LINE register to control the 9-th bit (When the PBE,
EPE and SPE are set, the 9-th bit is transmitted 0 and when PBE and SPE are set and EPE is
cleared, the 9-th bit is transmitted 1).
The controller supports three operation modes: RS-485 Normal Multidrop Operation Mode (NMM),
RS-485 Auto Address Detection Operation Mode (AAD) and RS-485 Auto Direction Control
Operation Mode (AUD). Software can choose any operation mode by programming the
UART_ALTCTL register, and drive the transfer delay time between the last stop bit leaving the TX
FIFO and the de-assertion of by setting DLY (UART_TOUT [15:8]) register.
RS-485
Normal
(NMM)
In RS-485 Normal Multidrop Operation Mode (RS485NMM (UART_ALTCTL[8]) = 1), in first,
software must decide the data which before the address byte be detected will be stored in RX FIFO
or not. If software wants to ignore any data before address byte detected, the flow is set RXOFF
(UART_FIFO[8]) then enable RS485NMM (UART_ALTCTL[8]) and the receiver will ignore any data
until a next address byte is detected (bit 9 = 1) and the address byte data will be stored in the RX
FIFO. If software wants to receive any data before address byte detected, the flow is disables
Sep 9, 2019
ISD94100 Series Technical Reference Manual
RTSACTLV=0
RTSACTLV=1
(default)
Multidrop
Page 584 of 928
Set UART_MODEM[1]=1 by software
Active
Operation
Mode
Rev1.09

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