Figure 6.2-2 Nreset Reset Waveform; Table 6.2.2-1 Reset Value Of Registers - Nuvoton ISD94124BYI Technical Reference Manual

WDT_CTL 0x0700
except bit 1 and bit 7
WDT_ALTCTL 0x0000
WWDT_RLDCNT 0x0000
WWDT_CTL 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 -
WWDT_STATUS
0x0000
WWDT_CNT 0x3F
BS Reload
from
(FMC_ISPCTL[1])
CONFIG0
FMC_DFBA Reload
from
CONFIG1
CBS
Reload
from
(FMC_ISPSTS[2:1))
CONFIG0
VECMAP Reload
based on
(FMC_ISPSTS[23:9])
CONFIG0
Other Peripheral
Reset Value
Registers
FMC Registers Reset Value
Note: '-' means that the value of register keeps original setting.
6.2.2.1 nRESET Reset
nRESET is triggered by pulling nRESET pin low. nRESET pin is an asynchronous reset input pin
so that it can be used to reset the system any time.
Pull nRESET pin to < 0.3* V
voltage (> 0.7* V ) presented on nRESET pin for >66us can exit the reset state. See nRESET
DD
reset waveform in Figure 6.2-2.
After an nRESET reset, the PINRF bit (SYS_RSTSTS[1]) will be set, indicating the previous reset
source is an nRESET reset. Writing 1 to PINRF clears the bit.
nRESET
0.7 V
DD
0.3 V
DD
nRESET Reset
Sep 9, 2019
ISD94100 Series Technical Reference Manual
0x0700 0x0700 0x0700
0x0000 0x0000 0x0000
0x0000 0x0000 0x0000
0x0000 0x0000 0x0000
0x3F 0x3F 0x3F
Reload Reload Reload
from from from
CONFIG0 CONFIG0 CONFIG0
Reload Reload Reload
from from from
CONFIG1 CONFIG1 CONFIG1
Reload Reload Reload
from from from
CONFIG0 CONFIG0 CONFIG0
Reload Reload Reload
based on based on based on
CONFIG0 CONFIG0 CONFIG0

Table 6.2.2-1 Reset Value of Registers

for > 66us will reset the chip. Once entered reset state, only high
DD
66 us

Figure 6.2-2 nRESET Reset Waveform

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0x0700 - 0x0700
0x0000 - 0x0000
0x0000 - 0x0000
0x3F0800
0x0000 - 0x0000
0x3F - 0x3F
Reload - Reload
from from
CONFIG0 CONFIG0
Reload - Reload
from from
CONFIG1
CONFIG1
Reload - Reload
from from
CONFIG0 CONFIG0
Reload - Reload
based on based on
CONFIG0 CONFIG0
66 us
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
-
Rev1.09