Figure 6.8-4 Pwm Independent Mode Architecture Diagram - Nuvoton ISD94124BYI Technical Reference Manual

PWM0_BRAKE0
PWM0_BRAKE1
PWM0_CLK0
PWM0_CLK2
PWM0_CLK4

Figure 6.8-4 PWM Independent Mode Architecture Diagram

Sep 9, 2019
ISD94100 Series Technical Reference Manual
Interrupt events
Trigger events
Prescaler0 Counter0
16
12bits 16bits
16
Comparator0
16bits
Counter1
16
16bits
16
Comparator1
16bits
Prescaler2 Counter2
16
12bits 16bits
16
Comparator2
16bits
Counter3
16
16bits
16
Comparator3
16bits
Prescaler4 Counter4
16
12bits 16bits
16
Comparator4
16bits
Counter5
16
16bits
16
Comparator5
16bits
Note:
Page 406 of 928
Interrupt
i
IRQ_MUX
Generator
Trigger
t
EADC
Generator
a
Pulse Output
a
Generator0 Control0
PWM0_BRAKE0
PWM0_BRAKE1
a
Pulse Output
a
Generator1 Control1
PWM0_BRAKE0
PWM0_BRAKE1
a
Pulse Output
a
Generator2 Control2
PWM0_BRAKE0
PWM0_BRAKE1
a
Pulse Output
a
Generator3 Control3
PWM0_BRAKE0
PWM0_BRAKE1
a
Pulse Output
a
Generator4 Control4
PWM0_BRAKE0
PWM0_BRAKE1
a
Pulse Output
a
Generator5 Control5
PWM0_BRAKE0
PWM0_BRAKE1
denotes interrupt events
i
denotes trigger events
t
denotes interrupt, trigger and pulse generate events
a
i
PWM0_CH0
i
PWM0_CH1
i
PWM0_CH2
i
PWM0_CH3
i
PWM0_CH4
i
PWM0_CH5
Rev1.09