Nuvoton ISD91300 Series ARM Cortex-M0 SoC Manuals

Manuals and User Guides for Nuvoton ISD91300 Series ARM Cortex-M0 SoC. We have 1 Nuvoton ISD91300 Series ARM Cortex-M0 SoC manual available for free PDF download: Technical Reference Manual

Nuvoton ISD91300 Series Technical Reference Manual (466 pages)

ISD ARM Cortex-M0 SoC

Brand: Nuvoton | Category: Computer Hardware | Size: 4 MB

Table of Contents
2
List of Tables
12
General Description
13
Features
14
Abbreviations
18
Table 3-1 List of Abbreviations
18
Parts Information List and Pin Configuration
19
ISD91300 Product Selection Guide
19
Figure 4-1 ISD91300 Series Selection Code
19
Pin Configuration
20
ISD91300 Pin Diagram
20
Figure 4-2 ISD91300 LQFP 64-Pin Diagram
20
Pin Description
21
ISD91300 Pin Description
21
Block Diagram
26
ISD91300 Block Diagram
26
Figure 5-1 ISD91300 Block Diagram
26
Functional Description
27
ARM® Cortex™-M0 Core
27
Figure 6-1 Functional Controller Diagram
27
System Manager
29
Overview
29
System Reset
29
System Power Distribution
30
Figure 6-2 ISD91300 Power Distribution Diagram
30
System Memory Map
31
Table 6-1 Address Space Assignments for On-Chip Controllers
32
Register Map
33
Register Description
34
System Timer (SYST)
51
Nested Vectored Interrupt Controller (NVIC)
56
Table 6-2 Exception Model
57
Table 6-3 System Interrupt Map
58
Table 6-4 Vector Table Format
59
System Control
81
Clock Controller and Power Management Unit (PMU)
88
Overview
88
Figure 6-3 Clock Generator Block Diagram
88
System Clock &SYST Clock
89
Figure 6-4 System Clock Block Diagram
89
Figure 6-5 Systick Clock Control Block Diagram
89
Peripheral Clocks
90
Power Management
91
Register Map
96
Register Description
97
General Purpose I/O (GPIO)
113
Overview
113
Features
113
Basic Configuration
113
Functional Description
114
Figure 6-6 Push-Pull Output
114
Figure 6-7 Open-Drain Output
115
Figure 6-8 Quasi-Bidirectional I/O Mode
115
Register Map
117
Register Description
118
Brownout Detection and Temperature Alarm
129
Overview
129
Register Map
129
Register Description
130
I 2 C Serial Interface Controller
135
Overview
135
Features
135
Functional Description
135
Figure 6-9 I C Bus Timing
136
Figure 6-10 I 2 C Protocol
136
Figure 6-11 START and STOP Conditions
137
Figure 6-12 Bit Transfer on the I C Bus
137
Figure 6-13 Acknowledge on the I C Bus
138
Figure 6-14 Master Transmits Data to Slave
138
Figure 6-15 Master Reads Data from Slave
138
Figure 6-16 Control I C Bus According to Current I C Status
139
Figure 6-17 Master Transmitter Mode Control Flow
140
Figure 6-18 Master Receiver Mode Control Flow
141
Figure 6-19 Save Mode Control Flow
142
Figure 6-20 GC Mode
143
Figure 6-21 Arbitration Lost
144
Figure 6-22 I 2 C Data Shifting Direction
145
Table 6-5 I C Status Code Description
147
Figure 6-23 I 2 C Time-Out Count Block Diagram
148
Register Map
149
Register Description
150
PWM Generator and Capture Timer (PWM)
157
Overview
157
Features
158
Block Diagram
159
Figure 6-24 PWM Generator Clock Source Control
159
Figure 6-25 PWM Generator Architecture Diagram
159
Functional Description
160
Figure 6-26 Legend of Internal Comparator Output of PWM-Timer
160
Figure 6-27 PWM-Timer Operation Timing
161
Figure 6-28 PWM Double Buffering Illustration
162
Figure 6-29 PWM Controller Output Duty Ratio
163
Figure 6-30 Paired-PWM Output with Dead-Zone Generation Operation
163
Figure 6-31 Capture Operation Timing
164
Figure 6-32 PWM-Timer Interrupt Architecture Diagram
165
PWM0 Register Map
167
Register Description
169
PWM1 Register Map
186
Register Description
187
Real Time Clock (RTC)
202
Overview
202
Features
202
Block Diagram
203
Figure 6-33 RTC Block Diagram
203
Functional Description
204
Register Map
207
Register Description
208
Serial Peripheral Interface (SPI)
221
Overview
221
Features
221
Block Diagram
221
Figure 6-34 SPI Block Diagram
221
Functionaldescription
222
Figure 6-35 SPI Master Mode Application Block Diagram
222
Figure 6-36 SPI Slave Mode Application Block Diagram
222
Figure 6-37 32-Bit in One Transaction
223
Figure 6-38 Word Sleep Suspend Mode
224
Figure 6-39 Byte Reorder Function
225
Figure 6-40 Byte Orderin Memory
225
Figure 6-41 Byte Reorder in Memory
226
Figure 6-42 2-Bit System Architecture
228
Figure 6-43 2-Bit Transfer Mode (Slave Mode)
228
Figure 6-44 Bit Sequence of Dual Output Mode
229
Figure 6-45 Bit Sequence of Dual Input Mode
229
Figure 6-46 Quad Modesystem Architecture
230
Figure 6-47 Bit Sequence of Quad Output Mode
230
Figure 6-48 FIFO Mode Block Diagram
231
Timing Diagram
233
Figure 6-49 SPI Timing in Master Mode
233
Figure 6-50 SPI Timing in Master Mode (Alternate Phase of SPI Bus Clock)
233
Figure 6-51 SPI Timing in Slave Mode
234
Figure 6-52 SPI Timing in Slave Mode (Alternate Phase of SPI Bus Clock)
234
Programming Examples
235
Register Map
237
Register Description
238
Timer Controller (TIMER)
253
Overview
253
Features
253
Block Diagram
254
Figure 6-53 Timer Controller Block Diagram
254
Figure 6-54 Clock Source of Timer Controller
254
Functional Description
255
Figure 6-55 Continuous Counting Mode
256
Register Map
257
Register Description
258
Watchdog Timer (WDT)
263
Overview
263
Features
263
Block Diagram
264
Figure 6-56 Watchdog Timer Clock Control
264
Figure 6-57 Watchdog Timer Block Diagram
264
Functional Description
265
Table 6-6 Watchdog Timer Time-Out Interval Period Selection
265
Register Map
266
Register Description
267
UART Interface Controller (UART)
269
Overview
269
Features
269
Block Diagram
269
Figure 6-58 UART Clock Control Diagram
269
Figure 6-59 UART Block Diagram
270
Basic Configuration
271
Functional Description
271
Table 6-7 UART Interface Controller Pin
271
Table 6-8 UART Baud Rate Equation
271
Table 6-9 UART Controller Interrupt Source and Flag List in DMA Mode
272
Figure 6-60 Auto Flow Control Block Diagram
273
Table 6-10 Controller Interrupt Source and Flag in Software Modelist
273
Figure 6-61 UART CTS Auto Flow Control Enabled
274
Figure 6-62 UART RTS Auto Flow Control Enabled
274
Figure 6-63 UART RTS Flow with Software Control
275
Figure 6-64 Irda Control Block Diagram
275
Figure 6-65 Irda TX/RX Timing Diagram
276
Figure 6-66 Structure of LIN Frame
277
Figure 6-67 Structure of LIN Byte
277
Register Map
279
Register Description
280
I 2 S Controller
297
S Controller (I S)Audio PCM Controller
297
Overview
297
Features
297
Block Diagram
298
Figure 6-68 I 2 S Controller Block Diagram
298
Functional Description
299
Figure 6-69 I 2 S Clock Control Diagram
299
Figure 6-70 I 2 S Data Format Timing Diagram
300
Figure 6-71 MSB Justified Data Format Timing Diagram
300
Figure 6-72 FIFO Contents for Various I
302
Figure 6-73 Master Mode Interface
303
Figure 6-74 Slave Mode Interface
303
Register Map
304
Register Description
305
PDMA Controller (PDMA)
316
Overview
316
Features
317
Block Diagram
318
Figure 6-75 DMA Controller Block Diagram
318
Figure 6-76 CRC Generator Block Diagram
319
Functional Description
320
Register Map
322
Register Description
325
Flash Memory Controller (Fmc)
353
Overview
353
Features
353
Block Diagram
354
Figure 7-1 Flash Memory Control Block Diagram
354
Functionaldescription
355
Flash Memory Organization
355
Table 7-1 Memory Address Map
355
Figure 7-2 Flash Memory Organization
356
Boot Selection
357
Figure 7-3 Program Executing Range for Booting from APROM and LDROM
357
Data Flash (DATAF)
358
Figure 7-4 Flash Memory Structure
358
User Configuration
359
In-System-Programming (ISP)
362
Figure 7-5 Example Flow of Boot Selection by BS Bit
362
Table 7-2 ISP Command List
363
Table 7-3 Device ID Memory Size
363
Register Map
364
Register Description
365
Analog Signal Path Blocks
372
Audio Analog-To-Digital Converter (ADC)
372
Overview
372
Features
372
Block Diagram
372
Functional Description
372
Figure 8-1 ADC Signal Path Block Diagram
372
Figure 8-2 ADC Clock Control
373
Table 8-1 Sample Rates for Hclk=49.152Mhz
373
Table 8-2 Sample Rates for Hclk=32.768Mhz
373
Figure 8-3 SDADC Controller Interrupt
374
Table 8-3 Sample Rates for Hclk=24.576Mhz
374
Table 8-4 Sample Rates for Hclk=16.384Mhz
374
Register Map
376
Register Description
377
Audio Class D Speaker Driver (DPWM)
384
Overview
384
Features
384
Block Diagram
384
Functional Description
384
Figure 8-4 DPWM Block Diagram
384
Table 8-5 DPWM Sample Rates for Various HCLK
385
Register Map
386
Register Description
387
Analog Comparator (ACMP)
392
Overview
392
Features
392
Block Diagram
392
Figure 8-5 Analog Comparator Block Diagram
392
Functional Description
393
Figure 8-6 Comparator Controller Interrupt Sources
393
Figure 8-7 Comparator Hysteresis Function
393
Register Map
394
Register Description
395
Analog Functional Blocks
399
Overview
399
Features
399
VMID Reference Voltage Generation
399
Figure 8-8 VMID Reference Generation
399
GPIO Current Source Generation
400
Figure 8-9 GPIO Current Source Generation
400
LDO Power Domain Control
401
Figure 8-10 LDO Power Domain
401
Microphone Bias Generator
402
Figure 8-11 MICBIAS Block Diagram
402
Figure 8-12 MICBIAS Application Diagram
402
Analog Multiplexer
403
Figure 8-13 Analog Multiplexer Control Signals
403
Temperature Sensor Measurement
404
Table 8-6 Temperature Sensor Measurement
404
Programmable Gain Amplifier
405
Figure 8-14 PGA Signal Path Block Diagram
405
Figure 8-15 PGA Structure
405
Table 8-7 PGA Input Impedance Variation with Gain Setting
406
Capsense Relaxation Oscillator/Counter
407
Figure 8-16 Capsense Function Block Diagram
407
Oscillator Frequency Measurement and Control
409
Figure 8-17 Oscillator Frequency Measurement Block Diagram
409
Figure 8-18 Example SUPERFINE Trim Frequency Adjustment
410
Figure 8-19 Typical Oscillator Frequency Versus SYS_IRCTCTL Setting
410
Register Map
411
Register Description
412
Automatic Level Control (ALC)
430
Overview
430
Block Diagram
430
Figure 8-20 ALC Block Diagram
430
Basic Configuration
431
Functional Description
431
Figure 8-21 ALC Response Graph
431
Figure 8-22 ALC Normal Mode Operation
432
Figure 8-23 ALC Hold Time
432
Figure 8-24 ALC Limit Mode Operation
433
Figure 8-25 ALC Operation with Noise Gate Disabled
434
Figure 8-26 ALC Operation with Noise Gate Enabled
434
Register Map
436
Register Description
437
Biquad Filter (BIQ)
442
Overview
442
Basic Configuration
442
Functional Description
442
Register Map
444
Register Description
445
Application Diagram
449
Figure 9-1 Application Diagram
449
Electrical Characteristics
450
Absolute Maximum Ratings
450
Table 10-1 Absolute Maximum Ratings
450
DC Electrical Characteristics
451
Table 10-2 DC Electrical Characteristics
453
Operating Current Curve (Test Condition: Run NOP)
454
Figure 10-1 Operating Current Curve
454
AC Electrical Characteristics
455
External 32Khz XTAL Oscillator
455
Internal 49.152Mhz Oscillator
455
Internal 16Khz Oscillator
455
Table 10-3 External 32Khz XTAL Oscillator
455
Table 10-4 Internal 49.152Mhz Oscillator
455
Table 10-5 Internal 16 Khz Oscillator
455
Analog Characteristics
456
Specification of ADC and Speaker Driver
456
Table 10-6 Specification of ADC and Speaker Driver
456
ADC Filter Characteristics
457
Figure 10-2 ADC Filter Characteristics
457
Figure 10-3 ADC Filter Characteristics Zoom in
458
Specification of PGA and BOOST
459
Table 10-7 Specification of PGA and BOOST
459
Specification of ALC an MICBIAS
460
Table 10-8 Specification of ALC an MICBIAS
460
Specification of LDO & Power Management
461
Specification of Brownout Detector
461
Table 10-9 Specification of LDO & Power Management
461
Specification of Power-On Reset (VCCD)
462
Specification of Temperature Sensor
462
Specification of Comparator
462
Table 10-10 Specification of Brownout Detector
462
Table 10-11 Specification of Power-On Reset (VCCD)
462
Table 10-12 Specification of Temperature Sensor
462
Table 10-13 Specification of Comparator
463
Package Dimensions
464
LQFP (7X7X1.4Mm Footprint 2.0Mm)
464
Revision History
466

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