Figure 6.7-23 Pwm 0% To 100% Duty Cycle In Up Count Type And Up-Down Count Type; Table 6.7.6-2 Pwm Pulse Generation Event Priority In Down Count Type; Table 6.7.6-3 Pwm Pulse Generation Event Priority In Up-Down Count Type - Nuvoton ISD94124BYI Technical Reference Manual

Priority Period and CMPD point event
1 (High)
2 (Low)

Table 6.7.6-2 PWM Pulse Generation Event Priority in Down Count Type

Priority CMPU And CMPU Point Event
1 (High)
2 (Low)

Table 6.7.6-3 PWM Pulse Generation Event Priority in Up-Down Count Type

According to event priority limitation, PWM generator can support 0% and 100% duty cycle PWM
output waveform only in up count and up-down count type. Figure 6.7-23 is an example about PWM
duty cycle from 0% to 100% in up count type and up-down count type where PERIOD is 4 with
different CMP value.
PWM period
CMPU = L
Zero = H
2
1
0
CMPDAT=0, 0% Duty
CMPDAT=1, 20% Duty
CMPDAT=2, 40% Duty
CMPDAT=3, 60% Duty
CMPDAT=4, 80% Duty
CMPDAT>4,100% Duty

Figure 6.7-23 PWM 0% to 100% Duty Cycle in Up Count Type and Up-Down Count Type

6.7.6.11 PWM Output Mode
The PWM supports two output modes: independent mode which may be applied to DC motor
system, complementary mode with dead-time insertion which may be used in the application of AC
induction motor and permanent magnet synchronous motor.
6.7.6.12 Independent mode
When OUTMODE (TIMERx_PWMCTL[16]) bit is set to 0, PWM output operates in independent
mode. In this mode, both PWMx_CH0 and PWMx_CH1 can output the same waveform as shown
Sep 9, 2019
ISD94100 Series Technical Reference Manual
(CMP = PERIOD)
Compare down event
Period event
(CMP = PERIOD)
Compare down event
Compare up event
PWM period
4 4
CMPU = L
3 3
CMPD = H
2
1
0
CMPDAT=0, 0% Duty
CMPDAT=1, 25% Duty
CMPDAT=2, 50% Duty
CMPDAT=3, 75% Duty
CMPDAT=4, 100% Duty
Page 357 of 928
PWM output
High
Low
PWM Output
High
Low
PWM period PWM period
4
3 3 3
2 2 2
1 1 1
0 0
4
3
2
1
0
Rev1.09