Basic Configuration; Functional Description; Figure 6.6-2 Descriptor Table Entry Structure - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc
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6.6.4

Basic Configuration

Clock source configuration
Enable PDMA controller clock in PDMACKEN (CLK_AHBCLK [1]).
Reset configuration
Reset PDMA controller in PDMARST (SYS_IPRST0[2]).
6.6.5

Functional Description

The PDMA controller transfers data from one address to another without CPU intervention. The
PDMA controller supports 16 independent channels and serves only one channel at one time, as
the result, PDMA controller supports two level channel priorities: fixed and round-robin priority,
PDMA controller serves channel in order from highest to lowest priority channel. The PDMA
controller supports two operation modes: Basic mode and Scatter-gather mode. Basic mode is used
to perform one descriptor table transfer. Scatter-gather mode has more entries for each PDMA
channel, and thus the PDMA controller supports sophisticated transfer through the entries. The
descriptor table entry data structure contains many transfer information including the transfer
source address, transfer destination address, transfer count, burst size, transfer type and operation
mode. The Figure 6.6-2 shows the diagram of descriptor table (DSCT) data structure.
0xF0
0xE0
0xD0
0x50
0x40
0x30
0x20
0x10
0x00
PDMA controller also supports single and burst transfer type and the request source can be from
software or peripheral request, transfer between memory to memory using software request. A
single transfer means that software or peripheral is ready to transfer one data (every data needs
one request), and the burst transfer means that software or peripherals will transfer multiple data
(multiple data only need one request).
6.6.5.1
Channel Priority
The PDMA controller supports two level channel priorities including fixed and round-robin priority.
The fixed priority channel has higher priority than round-robin priority channel. If multiple channels
are set as fixed or round-robin priority, the higher channel will have higher priority. The priority order
Sep 9, 2019
ISD94100 Series Technical Reference Manual
DSCT15
DSCT14
DSCT13
.
.
.
.
.
.
DSCT5
DSCT4
Descriptor Table Entry Structure
DSCT3
DSCT2
DSCT1
DSCT0
Descriptor Table

Figure 6.6-2 Descriptor Table Entry Structure

Page 265 of 928
DSCT_NEXT
0x0C
DSCT_DA
0x08
DSCT_SA
0x04
DSCT_CTL
0x00
Rev1.09

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