Figure 6.13-4 Bit Transfer On The I C Bus; Figure 6.13-5 Acknowledge On The I C Bus - Nuvoton ISD94124BYI Technical Reference Manual

START (S) and Repeated START (Sr) conditions are functionally identical. By generating Repeated
START (Sr) condition, a master can transmit and/or receive data from the same slave or different
slaves without releasing the bus.
6.13.5.1.2 STOP signal
I2C data flow follows the direction indicated by the R/W bit in addressing byte. The receiver (master
or slave) should acknowledge each received byte on the 9th SCL clock cycle.
•
If the slave signals a Not Acknowledge (NACK), the master can generate a STOP condition to
abort the data transfer or generate a Repeated START condition and start a new transmission.
•
If the master, as a receiving device, does Not Acknowledge (NACK) the slave, the slave
releases the SDA line for the master to generate a STOP or Repeated START condition.
SCL
SDA
SCL from
master
Data output by
transmitter
Data output
by receiver
Sep 9, 2019
ISD94100 Series Technical Reference Manual
Change of data
Data line stable;
allowed
data valid
Figure 6.13-4 Bit Transfer on the I
1
S
START
condition
Figure 6.13-5 Acknowledge on the I
Page 621 of 928
2
C Bus
Clock pulse for
acknowledgement
2 8
not acknowlegde
acknowlegde
2
C Bus
9
Rev1.09