Timing Diagram; Figure 6.14-34 Fifo Contents For Various I S Modes; Figure 6.14-35 Spi Timing In Master Mode - Nuvoton ISD94124BYI Technical Reference Manual

Figure 6.14-34 FIFO Contents for Various I

6.14.6 Timing Diagram

The active state of slave selection signal can be defined by setting the SSACTPOL
(SPIn_SSCTL[2]). The SPI clock which is in idle state can be configured as high or low state by
setting the CLKPOL (SPIn_CTL[3]). It also provides the bit length of a transaction word in DWIDTH
(SPIn_CTL[12:8]), and transmitting/receiving data from MSB or LSB first in LSB (SPIn_CTL[13]).
User can also select which edge of SPI clock to transmit/receive data in TXNEG/RXNEG
(SPIn_CTL[2:1]). Four SPI timing diagrams for master/slave operations and the related settings are
shown below.
SSACTPOL=1
SPIx_SSy pin
SSACTPOL=0
CLKPOL=0
SPIx_CLK pin
CLKPOL=1
SPIx_MOSIz pin
SPIx_MISOz pin
Note:
Master Mode
Registers Setting: SLAVE=0, LSB=0, DWIDTH=0x08
CLKPOL=0, TXNEG=1, RXNEG=0 or CLKPOL=1, TXNEG=0, RXNEG=1
x: Set number (x = 0, 1, 2), y: Slave select channel number in SPI0 (y = 0, 1),
z: MOSI and MISO channel number in SPI0 (z = 0)
SSACTPOL=1
SPIx_SSy pin
SSACTPOL=0
CLKPOL=0
SPIx_CLK pin
CLKPOL=1
SPIx_MOSIz pin
SPIx_MISOz pin
Note:
Master Mode
Registers Setting: SLAVE=0, LSB=1, DWIDTH=0x08
CLKPOL=0, TXNEG=0, RXNEG=1 or CLKPOL=1, TXNEG=1, RXNEG =0
x: Set number (x = 0, 1, 2), y: Slave select channel number in SPI0 (y = 0, 1),
z: MOSI and MISO channel number in SPI0 (z = 0)
Sep 9, 2019
ISD94100 Series Technical Reference Manual
MSB
TX[6] TX[5]
TX[7]
MSB
RX[6] RX[5]
RX[7]

Figure 6.14-35 SPI Timing in Master Mode

LSB
TX[1] TX[2]
TX[0]
LSB
RX[1] RX[2]
RX[0]
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S Modes
TX[4] TX[3] TX[2] TX[1]
RX[4] RX[3] RX[2] RX[1]
TX[3] TX[4] TX[5]
RX[3] RX[4] RX[5]
LSB
TX[0]
LSB
RX[0]
MSB
TX[6]
TX[7]
MSB
RX[6]
RX[7]
Rev1.09