Register Description - Nuvoton ISD94124BYI Technical Reference Manual

6.19.7 Register Description

DMIC Control Register (DMIC_CTL)
Offset
Register
DMIC_CTL
DMIC_BA+0x00
31 30
23 22
15 14
7 6
Reserved
Bits Description
[31:10] Reserved
[9] LCHEDGE23
[8] LCHEDGE01
[7] Reserved
[6:4] OSR
Sep 9, 2019
ISD94100 Series Technical Reference Manual
R/W Description
R/W DMIC Control Register
29 28
Reserved
21 20
Reserved
13 12
Reserved
5 4
OSR CHEN3
Reserved. Any values read should be ignored. When writing to this field always write
with reset value.
Channel 23 Data Latch Edge
The data of DMIC channel 2 and channel 3 is latched on DMIC_DATA1 pin. This bit is
used to select the data of DMIC channel 2 and channel 3 is latched on rising or falling
edge of DMIC_CLK (DMIC bus clock).
0 = The data of channel 2 is latched on falling edge of DMIC_CLK. The data of channel
3 is latched on rising edge of DMIC_CLK.
1 = The data of channel 2 is latched on rising edge of DMIC_CLK. The data of channel
3 is latched on falling edge of DMIC_CLK.
Channel 01 Data Latch Edge
The data of DMIC channel 0 and channel 1 is latched on DMIC_DATA0 pin. This bit is
used to select the data of DMIC channel 0 and channel 1 is latched on rising or falling
edge of DMIC_CLK (DMIC bus clock).
0 = The data of channel 0 is latched on falling edge of DMIC_CLK. The data of channel
1 is latched on rising edge of DMIC_CLK.
1 = The data of channel 0 is latched on rising edge of DMIC_CLK. The data of channel
1 is latched on falling edge of DMIC_CLK.
Reserved. Any values read should be ignored. When writing to this field always write
with reset value.
OSR Setting
000 = Down sample 32
001 = Down sample 64
010 = Down sample 128
011 = Down sample 256
100 = Down sample 100 or 50
Others = Reserved. Do not use.
Page 872 of 928
27 26 25
19 18 17
11 10 9
LCHEDGE23
3 2 1
CHEN2 CHEN1
Reset Value
0xB7CD_0000
24
16
8
LCHEDGE01
0
CHEN0
Rev1.09