Register Description - Nuvoton ISD94124BYI Technical Reference Manual

6.13.7 Register Description

I2C Control Register
(I2C_CTL)
Offset
Register
I2C_CTL I2Cn_BA+0x00
31 30
23 22
15 14
7 6
INTEN I2CEN
Description
Bits
[31:8]
Reserved
[7]
INTEN
[6] I2CEN
STA
[5]
[4] STO
[3] SI
[2] AA
Sep 9, 2019
ISD94100 Series Technical Reference Manual
R/W Description
2
R/W I C Control Register 0
29 28
Reserved
21 20
Reserved
13 12
Reserved
5 4
STA STO
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
Enable Interrupt
2
0 = I C interrupt Disabled.
2
1 = I C interrupt Enabled.
2
I C Controller Enable Bit
2
Set to enable I C serial function controller. When I2CEN=1 the I
The multi-function pin function must set to SDA, and SCL of I
2
0 = I C controller Disabled.
2
1 = I C controller Enabled.
2
I C START Control
Setting STA to logic 1 to enter Master mode, the I
START condition to bus when the bus is free. This bit will be cleared by hardware
automatically.
2
I C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I
check the bus condition if a STOP condition is detected. This bit will be cleared by hardware
automatically.
2
I C Interrupt Flag
2
When a new I C state is present in the I2C_STATUS register, the SI flag is set by hardware.
If bit INTEN (I2C_CTL [7]) is set, the I
software. Clear SI by writing 1 to this bit.
For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to
confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
Assert Acknowledge Control
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27 26 25
19 18 17
11 10 9
3 2 1
SI AA
2
C serial function enable.
2
C function first.
2
C hardware sends a START or repeat
2
C interrupt is requested. SI must be cleared by
Reset Value
0x0000_0000
24
16
8
0
Reserved
2
C controller will
Rev1.09