Flash Memory Controller (Fmc); Overview; Features - Nuvoton ISD94124BYI Technical Reference Manual

6.4

Flash Memory Controller (FMC)

6.4.1

Overview

The ISD94100 Series provides up to 512 KB of on-chip embedded flash for application program
memory (APROM) and data flash. In-System-Programming (ISP) and In-Application-Programming
(IAP) enables user to update chip embedded flash when chip is soldered on PCB. After chip
®
powers-on, Cortex -M4 CPU fetches code from APROM or LDROM depending on the boot select
(CBS) configuration in CONFIG0. The ISD94100 Series also provides Data Flash for user to store
some application dependent data to be retained when chip is powered off.
The ISD94100 Series supports configurable data flash size. The data flash size is decided by data
flash enable (DFEN) in CONFIG0 and data flash base address (DFBA) in CONFIG1. When DFEN
is set to 1, the data flash size is zero. When DFEN is set to 0, the APROM and data flash share
512 KB continuous address and the start address of data flash is defined by (DFBA) in CONFIG1.
6.4.2

Features


Supports up to 512 KB of application ROM (APROM).

Supports 4 KB loader ROM (LDROM).

Supports Data Flash with configurable memory size.

Supports 12 bytes User Configuration block to control system initiation.

Supports 4 KB page erase for all embedded flash.

Supports 32-bit/64-bit and multi-word flash programming function.

Supports fast flash programming verification function.

Supports CRC32 checksum calculation function.

Supports flash all one verification function

Supports cache memory to improve flash access performance and reduce power
consumption.

Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded flash memory.

Supports cache memory to improve flash access performance and reduce power
consumption.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
Page 191 of 928 Rev1.09