Figure 6.19-3 Typical Connection To Two Digital Microphones Sharing A Common Data Line; Figure 6.19-4 Digital Microphone Interface Timing Diagram - Nuvoton ISD94124BYI Technical Reference Manual

VDD

Figure 6.19-3 Typical connection to two digital microphones sharing a common data line

DMIC Bus Clock on DMIC_CLK0 pin
Digital MIC0 PDM data output
Digital MIC1 PDM data output
PDM data on DMIC_DAT0 pin
(Digital MIC0/1 output interleaved)

Figure 6.19-4 Digital Microphone Interface Timing Diagram

6.19.5.5 FIFO Operation
FIFO bits is 24 bits. ISD94100 series supports four channel digital microphone inputs, each channel
can be enabled by register CHENn (DMIC_CTL[3:0]) (n = 0, 1, 2 and 3). The memory arrangements
of PCM data for various settings are shown in Figure 6.19-5.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
SEL CLK
Digital MIC
DAT
SEL CLK
Digital MIC
DAT
MIC0
Data
High Z
MIC0
Data
Note: MIC0 PDM data for DMIC channel 0 and MIC1 PDM data for DMIC
channel 1 when LCHEDGE01 (DMIC_CTL[8]) = 0
Page 869 of 928
DMIC_CLKn
DMIC_DATn
Note: n = 0 or 1
Latched PDM Data on Falling Clock Edge
Latched PDM Data on Rising Clock Edge
High Z MIC0 High Z
Data
High Z
MIC1 MIC1
Data
Data
MIC1 MIC0 MIC1
Data Data Data
Rev1.09