Table 6.4.4-5 Flash Access Optimized Cycle Under Auto-Tuning Function - Nuvoton ISD94124BYI Technical Reference Manual

6.4.4.9 Flash Access Cycle Auto-Tuning
The ISD94100 series supports the flash access cycle auto-tuning function. User don't need to set
the flash access cycle by manual while system clock (HCLK) is changed, hardware will monitor the
HCLK frequency and generate a optimized cycle number for flash controller to get the best
performance.
Any updated registers of HCLK source and divder, are the auto-tuning trigger events, include
HCLKSEL(CLK_CLKSEL0), CLK_PLLCTL, and HCLKDIV(CLK_CLKDIV0). When detecting a
event, FMC will set the max number (i.e., 8) temporarily to CYCLE (FMC_CYCCTL[3:0]) register to
save flash access without influence by clock changed. HIRC clock is necessary for auto-tuning to
generate a exact period for HCLK counting. The HCLK detected frequency and optimized CYCLE
number is showed in Table 6.4.4-5.
HCLK Clock Frequency
0 MHz ~27 MHz
27 MHz~51 MHz
51 MHz~78 MHz
78 MHz~105 MHz
105 MHz~132 MHz
132 MHz~159 MHz
159 MHz~189 MHz
>189 MHz

Table 6.4.4-5 Flash Access Optimized Cycle under auto-tuning function

The flash access cycle auto-tuning flow is showed in Figure 6.4-17.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
Page 212 of 928
Optimized CYCLE Number
1
2
3
4
5
6
7
8
Rev1.09