Figure 6.7-3 Pwm Generator Overview Block Diagram; Figure 6.7-4 Pwm System Clock Source Control - Nuvoton ISD94124BYI Technical Reference Manual

PCLK0/1
TMR0
TMR1
TMR2
TMR3
In PWM mode, the timer clock source, i.e. now the PWM system clock, TMR0_CLK and TMR1_CLK
clock sources are fixed to be from PCLK0; TMR2_CLK and TMR3_CLK clock sources are fixed to be
from PCLK1, shown in Figure 6.7-4 .
Further, the PWM counter (TIMERx_PWMCLK) clock source can be selected from TMRx_CLK (PWM
system clock ) or Timer interrupt events (TMRx_INT) as shown in Figure 6.7-5.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
TIMERx_PWM

Figure 6.7-3 PWM Generator Overview Block Diagram

TMR0CKEN (CLK_APBCLK0[2])
TMR1CKEN (CLK_APBCLK0[3])
PCLK0
TMR2CKEN (CLK_APBCLK0[4])
TMR3CKEN (CLK_APBCLK0[5])
PCLK1

Figure 6.7-4 PWM System Clock Source Control

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NVIC
TMx, x=0~3
(PWMx_CH0)
TMx_EXT, x=0~3
(PWMx_CH1)
TMR0_CLK
TMR1_CLK
TMR2_CLK
TMR3_CLK
Rev1.09