Block Diagram; Basic Configuration; Figure 6.17-1 I 2 S Controller Block Diagram - Nuvoton ISD94124BYI Technical Reference Manual

6.17.3 Block Diagram

Generator
APB
Interface
&
dma_req
Control
Registers
dma_ack

6.17.4 Basic Configuration


Clock source configuration
–
Select the source of I
–
2
Enable I S peripheral clock in I2SCKEN (CLK_APBCLK0[29]).

Reset configuration
–
Reset I 2 S controller in I2SRST (SYS_IPRST1[29]).

Pin configuration
Pin Name
Group
I2S0_BCLK
I2S0_DI
I2S0
I2S0_DO
I2S0_LRCK
I2S0_MCLK
Sep 9, 2019
ISD94100 Series Technical Reference Manual
I2S Clock
Transmit
Contrl
Tx Shift Register
&
TXFIFO
Receive
Control
&
Rx Shift Register
RXFIFO
Slave
2
Figure 6.17-1 I S Controller Block Diagram
2 S peripheral clock on I2SSEL (CLK_CLKSEL3[17:16]).
GPIO
PD.0
PD.6
PB.13
PD.4
PB.14
PD.5
PD.1
PD.3
PB.15
PD.2
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MUX
Shift Clock
MUX
I2S_MCLK
I2S_LRCLK
I2S_DO
I2S_BCLK
I2S_DI
MFP
MFP4
MFP3
MFP2
MFP4
MFP2
MFP3
MFP4
MFP3
MFP2
MFP3
Rev1.09