Functional Description - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc

Table of Contents

6.21.5 Functional Description

The DPWM block receives audio data by writing PCM audio to the FIFO. FIFO is accessed through

PDMA for ease of streaming. The audio stream is sampled by a zero-order hold and fed to an

upsmaple filter. The signal is then modulated and sent to the driver stage through a non-overlap

circuit. Master clock rate of the Delta-Sigma modulator is controlled by DPWM_CLK. This clock is

generated by the internal system clock.

6.21.5.1 DPWM Clock Generation

(CLK_CLKSEL2[13:12]). The DPWM clock control diagram is shown in Figure 6.21-2. Note that the

frequency of DPWM_CLK must be 512 fs (Sample rate) or 500 fs according to the value of register

CLKSET (DPWM_CTL[31]).

DPWMSEL (CLK_CLKSEL2[13:12])

ISD94100 Series Technical Reference Manual

DPWMCKEN (CLK_APBCLK1[6])

1/(CLKDIV + 1)

CLKDIV = DPWM_ZOHDIV[15:8]

Note: Before clock switching, both the pre-selected and newly

selected clock sources must be turned on and stable.

Page 898 of 928

Show Quick Links

Table of Contents