6.4.3
Block Diagram
The flash memory controller consists of AHB slave interface, ISP control logic and flash macro
interface timing control logic. The block diagram of flash memory controller is shown as follows.
Cortex-M4 I-BUS / D-BUS
Flash Memory Controller
AHB Slave Interface
Cache Memory
Controller
Cache Memory
(4KB)
BANK0
Application ROM
with Data Flash
Figure 6.4-1 Flash Memory Controller Block Diagram
Sep 9, 2019
ISD94100 Series Technical Reference Manual
Flash
Operation
Controller
Embedded Flash Memory
(512KB)
Page 192 of 928
Cortex-M4 S-BUS
AHB Slave Interface
Flash
Control
Registers
Flash Initialization
Controller
User Configuration
(4KB)
Loader ROM
(LDROM 4KB)
Rev1.09