Figure 6.8-25 Pwm Synchronous Function With Synchronize Source From Sync_In Signal; Figure 6.8-26 Pwm0_Ch0 Output Control In Independent Mode - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc
Table of Contents

Advertisement

CH0_PERIOD = 900
CH0_PERIOD = 600
PHSDIR0 = 1
(PWM_SYNC[24])
PHS = 0
(PWM_PHS0)
PWM SYNC input
PWM_CH0
CH2_PERIOD = 900
CH2_CMPDAT = 600
PHSDIR2 = 0
(PWM_SYNC[25])
PHS = 600
(PWM_PHS2)
PWM_CH2
CH4_PERIOD = 900
CH4_CMPDAT = 600
PHSDIR4 = 1
(PWM_SYNC[26])
PHS = 600
(PWM_PHS4)
PWM_CH4

Figure 6.8-25 PWM Synchronous Function with Synchronize source from SYNC_IN Signal

6.8.5.20 PWM Output Control
After PWM pulse generation, there are four to six steps to control the output of PWM channels. In
independent mode, there are Mask, Brake, Pin Polarity and Output Enable four steps as shown in
Figure 6.8-26. In complementary mode, it needs two more steps to precede these four steps,
Complementary channels and Dead-Time Insertion as shown in Figure 6.8-27.
MSKEN0
(PWM_MSKEN[0])
Pulse
Generation

Figure 6.8-26 PWM0_CH0 Output Control in Independent Mode

Sep 9, 2019
ISD94100 Series Technical Reference Manual
PWM period
PWM period
PWM period
PWM period
Mask
Brake
PWM_BRKCTL0_1[15:0]
Mask Data
MSKDAT0
BRKAEVEN
(PWM_MSK[0])
(PWM_BRKCTL0_1[17:16])
Independent Mode 4 Steps
Page 425 of 928
PWM period
PWM period
PWM period
PWM period
Note:
SYNC PHS & PHSDIR Load
Polarity
Enable
PINV0
POEN0
(PWM_POLCTL[0])
(PWM_POEN[0])
Brake
PWM period
PWM0_CH0
Rev1.09

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents