Figure 6.4-4 Boot From Ldrom With Iap Support; Table 6.4.4-2 Boot Configuration - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc

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Running mode

LDROM with IAP

LDROM without IAP

APROM with IAP

APROM without IAP

Boot from LDROM with IAP support

By writing 0b00 into CBS[1:0] bits in CONFIG0, the ISD94100 device will map the system vector

table into LRDOM space, which has physical memory address from 0x0100_0000 - 0x0100_01FF.

In other words, MCU will no longer load the vector value from APROM address 0x0000_0000 to

0x0000_01FF, it loads the vector values from LDROM space 0x0010_0100 to 0x0010_01FF.

In this mode, the MCU boots from LDROM, and has the access to all memory space, including

512KB APROM and 4KB LDROM. The device can read, erase and write other parts of the memory

so that the IAP function can be implemented.

This mode supports dynamic remapping so that APROM, LDROM or SRAM address can be

remapped into system vector table. Remapping can be achieved by first writing the target remap-

to address to FMC_ISPADDR register and then triggering ISP procedure with the "Vector Remap"

command (0x2E). The targeted remapping address needs to be in alignment with 512 bytes. In

VECMAP (FMC_ISPSTS[23:9]), shows the finial system vector mapping address.

ISD94100 Series Technical Reference Manual

Load System Vector table from

0x0010_0000 - 0x0010_01FF

0x0000_0000 - 0x0010_01FF

ApplicationROM

System Vector Table

Figure 6.4-4 Boot from LDROM with IAP support

Page 196 of 928

Support Vector Re-Mapping

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