Peripheral Clock; Power-Down Mode Clock; Clock Output; Figure 6.3-6 Clock Output Block Diagram - Nuvoton ISD94124BYI Technical Reference Manual

6.3.4

Peripheral Clock

Each peripheral module can have its own clock source selection and configuration, please refer to
CLK_CLKSEL1 and CLK_CLKSEL2 register description for more detailed information.
6.3.5

Power-down Mode Clock

Different power down modes have different impact on the system clocks. Under a certain power
down mode, some clock sources (including system clocks and peripheral clocks) are disabled
while some other clock sources are still available. However regardless the power down mode the
following clocks are always available:

Clock Generator

10 kHz internal low speed RC oscillator (LIRC) clock

32.768 kHz external low speed crystal oscillator (LXT) clock

Peripheral Clock which uses LXT or LIRC as clock source
6.3.6

Clock Output

The ISD94100 series device is equipped with a power-of-2 frequency divider which is composed of
16 chained divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to
one multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2
divided clocks with the frequency from F
divider.
The output formula is F
output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing
0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches
low state and stays in low state.
CLKOEN
(CLK_CLKOCTL[4])
HIRC
11
HCLK
10
LXT
01
HXT
00
CLKOSEL (CLK_CLKSEL1[29:28])
LIRC
LXT
Sep 9, 2019
ISD94100 Series Technical Reference Manual
1
/2 to F /2
in in
(N+1)
= F /2 , where F is the input clock frequency, F
in
out in
Enable
divide-by-2 counter
16 chained
divide-by-2 counter
2 3
1/2 1/2 1/2 ......
RTCSEL(CLK_CLKSEL3[8])
/10000
1
/32768 0

Figure 6.3-6 Clock Output Block Diagram

Page 145 of 928
16
where F is input clock frequency to the clock
in
FREQSEL
(CLK_CLKOCTL[3:0])
DIV1EN
15 16
1/2 1/2
(CLK_CLKOCTL[5])
0000
0001
: 16 to 1
0
: MUX
1110
1
1111
1 Hz clock from RTC
is the clock divider
out
CLK1HZEN
(CLK_CLKOCTL[6])
0
CLKO
1
Rev1.09